參數(shù)資料
型號: IS43R16160A-6T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16Meg x 16 256-MBIT DDR SDRAM
中文描述: 16M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: PLASTIC, TSOP2-66
文件頁數(shù): 31/56頁
文件大?。?/td> 792K
代理商: IS43R16160A-6T
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
31
ISSI
IS43R16160A
IDD Max Specifications and Conditions
(0°C < TA < 70°C, VDDQ=2.5V+ 0.2V, VDD=2.5 +0.2V, for DDR400 device VDDQ=2.6V+ 0.1V, VDD=2.6 +0.1V)
Conditions
Version
Symbol
-5
-6
Unit
Operating current - One bank Active-Precharge;
tRC=tRCmin;tCK= tCK (min); DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
IDD0
120
110
mA
Operating current - One bank operation;
One bank open, BL=4
IDD1
160
140
25
45
44
52
50
30
90
80
25
mA
Precharge power-down standby current;
All banks idle; power - down mode; CKE = <VIL(max);
tCK= tCK (min); Vin = Vref for DQ,DQS and DM
IDD2P
30
mA
Precharge Floating standby current;
CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK= tCK (min); Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,
DQS and DM
IDD2F
mA
Precharge Quiet standby current;
CS# > = VIH(min); All banks idle; CKE > = VIH(min);
Address and other control inputs stable with keeping >= VIH(min) or =< VIL (max);
Vin = Vref for DQ ,DQS and DM
IDD2Q
mA
Active power - down standby current;
one bank active; power-down mode; CKE=< VIL (max);
Vin = Vref for DQ,DQS and DM
tCK = tCK (min);
IDD3P
mA
Active standby current;
CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge;
tRC=tRASmax; tCK = tCK (min); DQ, DQS and DM inputs changing twice per clock cycle; address
and other control inputs
changing once per clock cycle
IDD3N
mA
Operating current - burst read;
Burst length = 2; reads; continuous burst; One bank active; address
and control inputs changing once per clock cycle; CL=2 at tCK= tCK(min);
50% of data changing at every burst; lout = 0 m A
IDD4R
270
230
mA
Operating current - burst write;
Burst length = 2; writes; continuous burst; One bank active address
and control inputs changing once per clock cycle; CL=2 at tCK= tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle, 50% of input data changing at every burst
IDD4W
250
210
mA
Auto refresh current;
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A
& DDR266B at 133Mhz, 12*tCK for DDR333B; distributed refresh
IDD5
210
200
mA
Self refresh current;
CKE =< 0.2V; External clock should be on; tCK= tCK(min);
IDD6
3
3
mA
Operating current - Four bank operation;
Four bank interleaving with BL=4
IDD7
400
350
mA
tCK = tCK (min);
相關(guān)PDF資料
PDF描述
IS43R16160A 16Meg x 16 256-MBIT DDR SDRAM
IS43R16320A 32Meg x 16 512-MBIT DDR SDRAM
IS43R16320A-6TL 32Meg x 16 512-MBIT DDR SDRAM
IS43R16800A-6 8Meg x 16 128-MBIT DDR SDRAM
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