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參數(shù)資料
| 型號： | K4T1G044QQ-HC(L)E6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb Q-die DDR2 SDRAM Specification |
| 中文描述： | 1Gb的調(diào)Q DDR2內(nèi)存芯片規(guī)格 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 891K |
| 代理商： | K4T1G044QQ-HC(L)E6 |
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K4T1G084QQ
K4T1G164QQ
Rev. 1.01 November 2007
DDR2 SDRAM
22 of 44
K4T1G044QQ
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS
through a 20
to 10 k
resistor to insure proper operation.
5.
AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6.
All voltages are referenced to VSS.
7.
These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
8.
Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
t
DS
t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS
DQS
D
DMin
DQS/
DQS
DQ
DM
t
DH
Figure 3 - Data Input (Write) Timing
DMin
DMin
DMin
D
D
D
V
IL
(ac)
V
IH
(ac)
V
IL
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
V
IL
(dc)
V
IH
(dc)
t
CH
t
CL
CK
CK
CK/CK
DQS/DQS
DQ
DQS
DQS
t
RPST
Q
t
RPRE
t
DQSQmax
t
QH
t
QH
t
DQSQmax
Q
Q
Q
Figure 4 - Data Output (Read) Timing
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