參數(shù)資料
型號(hào): L80227
廠商: LSI CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: LQFP-64
文件頁數(shù): 120/158頁
文件大?。?/td> 1084K
代理商: L80227
Draft 6/5/00
6-22
Specifications
Copyright 1999 by LSI Logic Corporation. All rights reserved.
6.3.5 Link Pulse Timing Characteristics
Table 6.10
shows the Link Pulse AC timing parameters. See
Figure 6.14
and
Figure 6.15
for the Link Pulse timing diagrams.
Table 6.10
Link Pulse Timing
Sym
Parameter
Limit
Unit
Condition
Min
Typ
Max
t61
NLP Transmit Link Pulse
Width
See
Figure 2.7
ns
t62
NLP Transmit Link Pulse
Period
8
24
ms
t63
NLP Receive Link Pulse
Width Required For
Detection
50
ns
t64
NLP Receive Link Pulse
Minimum Period Required
For Detection
6
7
ms
link_test_min
t65
NLP Receive Link Pulse
Maximum Period Required
For Detection
50
150
ms
link_test_max
t66
NLP Receive Link Pulses
Required To Exit Link Fail
State
3
3
3
Link
Pulses
lc_max
t67
FLP Transmit Link Pulse
Width
100
150
ns
t68
FLP Transmit Clock Pulse To
Data Pulse Period
55.5
62.5
69.5
ms
interval_timer
t69
FLP Transmit Clock Pulse To
Clock Pulse Period
111
125
139
ms
t70
FLP Transmit Link Pulse
Burst Period
8
22
ms
transmit_link_burst
_timer
t71
FLP Receive Link Pulse
Width Required For
Detection
50
ns
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