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參數(shù)資料
| 型號： | L80227 |
| 廠商： | LSI CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 54/158頁 |
| 文件大小： | 1084K |
| 代理商： | L80227 |
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Draft 6/5/00
2-34
Functional Description
Copyright 1999 by LSI Logic Corporation. All rights reserved.
2.4 Start of Packet
This section describes start of packet operation for both the 100 Mbits/s
and 10 Mbits/s modes.
2.4.1 100 Mbits/s
A unique Start of Stream Delimiter (SSD) indicates the start of packet for
100 Mbits/s mode. The SSD pattern consists of two /J/K/ 5B symbols
inserted at the beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24 and shown in
Table 2.5
and
Figure 2.2
.
The 4B5B encoder generates the transmit SSD and inserts the /J/K/
symbols at the beginning of the transmit data packet in place of the first
two 5B symbols of the preamble, as shown in
Figure 2.2
.
The 4B5B decoder detects the receive pattern. To do this, the decoder
examines groups of 10 consecutive code bits (two 5B words) from the
descrambler. Between packets, the receiver detects the idle pattern
(5B /I/ symbols). When in the idle state, the device deasserts the CRS
and RX_DV pins.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of the /J/K/ symbols, the start of packet is detected, data
reception begins, and /5/5/ symbols are substituted in place of the /J/K/
symbols.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver are a pattern that is neither /I/I/ nor /J/K/ symbols, but contain
at least two noncontiguous zeros, activity is detected but the start of
packet is considered to be faulty and a False Carrier Indication (also
referred to as bad SSD) is signaled to the controller interface.
When False Carrier is detected, CRS is asserted, RX_ER is asserted,
RX_DV remains deasserted, and the RXD[3:0] output state is 0b1110
while RX_ER is asserted.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but does
not contain at least two noncontiguous zeros, the data is ignored and the
receiver stays in the idle state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80227/B | 制造商:LSI Corporation 功能描述: 制造商:LSI Corporation 功能描述:L80227/B |
| L80227/BI | 制造商:LSI Corporation 功能描述:L80227/BI |
| L80227FR | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two |
| L80227-I | 制造商:LSI Corporation 功能描述:STD CELL ASIC |
| L80227-I-LEADFREE | 制造商:LSI Corporation 功能描述:796000124413 |
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