參數(shù)資料
型號: L80227
廠商: LSI CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: LQFP-64
文件頁數(shù): 88/158頁
文件大小: 1084K
代理商: L80227
Draft 6/5/00
4-16
Registers
Copyright 1999 by LSI Logic Corporation. All rights reserved.
4.3.7 Configuration Register (Register 17)
The default value for this register is 0xFF00.
PLED3_[1:0]n Programmable LED 3 Output Select
R/W [15:14]
PLED2_[1:0]n Programmable LED 2 Output Select
R/W [13:12]
15
14
13
12
11
10
9
8
PLED3_1n
PLED3_0n
PLED2_1n
PLED2_0n
PLED1_1n
PLED1_0n
PLED0_1n
PLED0_0n
7
4
3
2
1
0
LED_DEF1
LED_DEF0
APOL_DIS
JAB_DIS
MREG
Reserved
PLED3_1n PLED3_0n Meaning
1
1
Normal (PLED3n pin state is determined
from the LED_DEF[1:0] bits (default is
LINK100). 0b11 is the default for these
bits
LED tied to PLED3n blinks (toggles 100
ms LOW, then 100 ms HIGH)
LED tied to PLED3n ON steady (PLED3n
output LOW)
LED tied to PLED3n OFF steady
(PLED3n output HIGH)
1
0
0
1
0
0
PLED2_1n PLED2_0n Meaning
1
1
Normal (PLED2n pin state is determined
from the LED_DEF[1:0] bits (default is
Activity). 0b11 is the default for these bits
LED tied to PLED2n blinks (toggles 100
ms LOW, then 100 ms HIGH)
LED tied to PLED2n ON steady (PLED2n
output LOW)
LED tied to PLED2n OFF steady
(PLED2n output HIGH)
1
0
0
1
0
0
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