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參數(shù)資料
| 型號： | L80227 |
| 廠商： | LSI CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 140/158頁 |
| 文件大?。?/td> | 1084K |
| 代理商： | L80227 |
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Draft 6/5/00
A-6
Application Information
Copyright 1999 by LSI Logic Corporation. All rights reserved.
V
DD
and each of the TPO
±
outputs. Their value should be chosen to
provide the correct termination impedance when looking back through
the transformer from the twisted-pair cable, as shown in
Figure A.1
through
Figure A.3
. The value of these two external termination resistors
depends on the type of cable the device drives.
To minimize common mode output noise and to aid in meeting radiated
emissions requirements, it may be necessary to add a common mode
choke on the transmit outputs as well as add common mode bundle
termination. The qualified transformers mentioned in
Table A.2
all contain
common mode chokes along with the transformers on both the transmit
and receive sides, as shown in
Figure A.1
through
Figure A.3
. Common
mode bundle termination may be needed and can be achieved when the
unused pairs in the RJ45 connector are connected to chassis ground
through 75 ohm resistors and a 0.01
μ
F capacitor, as shown in
Figure A.1
through
Figure A.3
.
To minimize noise pickup into the transmit path in a system or on a PCB,
the loading on TPO
±
should be minimized and both outputs should
always be loaded equally.
A.3 TP Receive Interface
Receive data is typically transformer coupled into the receive inputs on
TPI
±
and terminated with external resistors as shown in
Figure A.1
through
Figure A.3
.
The transformer for the receiver should have a winding ratio of 1:1, as
shown in
Figure A.1
through
Figure A.3
. The specifications for this
transformer are shown in
Table A.1
and sources for the transformer are
listed in
Table A.2
.
The receive input must be terminated with the correct termination
impedance to meet the input impedance and return loss requirements of
IEEE 802.3. In addition, the receive TP inputs must be attenuated. Both
the termination and attenuation is accomplished with four external
resistors in series across the TPI
±
inputs, as shown in
Figure A.1
through
Figure A.3
. Each resistor should be 25% of the total series resistance,
and the total series resistance should be equal to the characteristic
impedance of the cable (100
for UTP). It is also recommended that a
0.01 Fcapacitor be placed between the center of the series resistor
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L8050HPLT1 | General Purpose Transistors NPN Silicon |
| L8050HPLT1G | General Purpose Transistors NPN Silicon |
| L8050HQLT1 | General Purpose Transistors NPN Silicon |
| L8050HQLT1G | General Purpose Transistors NPN Silicon |
| L8050LT1 | General Purpose Transistors NPN Silicon |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80227/B | 制造商:LSI Corporation 功能描述: 制造商:LSI Corporation 功能描述:L80227/B |
| L80227/BI | 制造商:LSI Corporation 功能描述:L80227/BI |
| L80227FR | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two |
| L80227-I | 制造商:LSI Corporation 功能描述:STD CELL ASIC |
| L80227-I-LEADFREE | 制造商:LSI Corporation 功能描述:796000124413 |
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