參數(shù)資料
型號: L80227
廠商: LSI CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: LQFP-64
文件頁數(shù): 94/158頁
文件大小: 1084K
代理商: L80227
D
5
M
R
C
Figure 5.1
MI Serial Port Frame Timing Diagram
WRITE Cycle
MDC
MDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
0
1
ST
OP
P4
P3
PHYAD
P2
P1
P0
R4
R3
REGAD
R2
R1
R0
1
0
TA
D15 D14 D13 D12 D11
DATA
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WRITE Bits
PHY clocks in data on rising edges of MDC with t
s
= 10 ns minimum and t
h
= 10 ns minimum
READ Cycle
MDC
MDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
1
0
ST
OP
P4
P3
PHYAD
P2
P1
P0
R4
R3
REGAD
R2
R1
R0
Z
0
TA
D15 D14 D13 D12 D11
DATA
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WRITE Bits
PHY clocks in data on rising edges of MDC with
t
s
= 10 ns minimum, and t
h
= 10 ns minimum
READ Bits
PHY clocks out data on rising edges of MDC with
t
d
= 20 ns maximum
Note: ST = start bits, OP = operation bits (read or write), PHAD = PHY address, REGAD = register address, TA = turnaround bits
For more detailed information on the timing related to t
s,
t
h, and
t
d,
please see Chapter 6, “Specifications.”
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
L80227/B 制造商:LSI Corporation 功能描述: 制造商:LSI Corporation 功能描述:L80227/B
L80227/BI 制造商:LSI Corporation 功能描述:L80227/BI
L80227FR 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two
L80227-I 制造商:LSI Corporation 功能描述:STD CELL ASIC
L80227-I-LEADFREE 制造商:LSI Corporation 功能描述:796000124413