參數(shù)資料
型號: L80227
廠商: LSI CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: LQFP-64
文件頁數(shù): 147/158頁
文件大小: 1084K
代理商: L80227
Draft 6/5/00
Serial Port
A-13
Copyright 1999 by LSI Logic Corporation. All rights reserved.
directly to the L80227 without any glue logic, as shown in
Figure A.1
through
Figure A.3
.
As described earlier, the MI serial port consists of six signals: MDC,
MDIO, and MDA[3:0]n. However, only two signals, MDC and MDIO, are
needed to shift data in and out. MDA[3:0]n are not needed, but are
provided for convenience only.
Note that the MDA[3:0]n addresses are inverted inside the L80227 before
going to the MI serial port block. This means that the MDAn[3:0] pins
would have to be pin strapped to 0b1111 externally to successfully match
the MI physical address of 0b00000 on the PHYAD[4:0] bits internally.
The MSB of the address is internally tied to zero.
A.8.1 Serial Port Addressing
Tying the MDA[3:0]n pins to the desired value selects the device address
for the MI serial port. MDA[3:0]n share the same pins as the LED
outputs, respectively, as shown in
Figure A.5
a. At powerup or reset, the
output drivers are 3-stated for an interval called the power-on reset time.
During the power-on reset interval, the value on these pins is latched into
the device, inverted, and used as the MI serial port address. The
PLED[5:2] outputs are open-drain with a pullup resistor and can drive
LEDs tied to V
DD
. The PLED[1:0] outputs have both pullup and pulldown
driver transistors with a pullup resistor, so the PLED[1:0] outputs can
drive LEDs tied to either V
DD
or GND.
If an LED is to be connected on an LED output, an LED and resistor are
tied to V
DD
as shown in
Figure A.4
b. If a HIGH address is desired, the
LED to V
DD
automatically makes the latched address value a HIGH. If a
LOW value for the address is desired, a 50 K
resistor to GND must be
added as shown in
Figure A.4
b.
If no LEDs are needed on the LED outputs, the selection of addresses
can be done as shown in
Figure A.4
c. If a HIGH address is desired, the
pin should be left floating and the internal pullup pulls the pin HIGH
during power-on reset time and latches in a HIGH address value. If a
LOW address is desired, the LED output pins should be tied either
directly to GND or through an optional 50 K
resistor to GND. The
PLED[1:0] outputs should always be tied through a 50 K
resistor to
GND since they have both pullup and pulldown capability.
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