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參數(shù)資料
| 型號： | LXP730 |
| 廠商： | Intel Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 22/70頁 |
| 文件大?。?/td> | 531K |
| 代理商： | LXP730 |
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LXP730
—
Multi-Rate DSL Framer
22
Datasheet
The burst frequency of the ADPI clocks is derived from MCLK and can be adjusted by the
SAPCLKDIV (bits 6 & 7, in register 17h, FIFO_MISC).
2.11
Modes of Operation
2.11.1
Microprocessor Control (MPC) Mode
The Microprocessor Control (MPC) mode provides access for a microprocessor to configure and
control the operation of the framer. The LXP730 provides an 8-bit data bus for the purpose of
reading and writing internal registers. The registers are used to configure framer settings, to read
and write the MDSL Overhead bits and to configure interrupts and other run-time operational
functions.
The microprocessor access circuits support both MOTEL (MOTorola/IntEL) microprocessor
interfaces. A chip select signal activates the interface between the device and the microprocessor.
In the Motorola mode, the LXP730 supports the R/W and CS signals. The Motorola signal DS is
not used in this mode. In the Intel mode, the LXP730 supports the CS, ALE, WR and RD signals.
In the Intel mode, the data pins conform to the Intel style Address/Data (AD) functionality. The
Table 4. Typical ADPLL Register Settings, MCLK = 16.384MHz
PCMCLK
Output
(MHz)
#B PCM
#B DSL
NCO Frequency
(MHz)
PROG_
DIV
NCOFREQ/
MCLK
CFREQ(17:0)
1.544
24
12
PCMCLK
×
8
PCMCLK
×
4
PCMCLK
×
8
PCMCLK
×
16
PCMCLK
×
16
PCMCLK
×
32
4
0.754
0x30400
2.048
32
18
2
0.5
0x20000
1.152
18
18
4
0.5625
0x24000
0.896
14
14
8
0.875
0x38000
0.768
12
12
8
0.75
0x30000
0.256
4
4
16
0.5
0x20000
Figure 3. Clock Generation and Distribution
NCO
÷
2
PCM
Clock
Select
Programmable Divider
(1E: 7 - 0)
Codec
Clock
Select
PCM Port (20: 6 - 5)
Codec Port (22: 7 - 6)
MCLK
(pin 8)
PCLK
(pin 14)
Divider
Clock
Select
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