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參數(shù)資料
| 型號： | LXP730 |
| 廠商： | Intel Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 24/70頁 |
| 文件大?。?/td> | 531K |
| 代理商： | LXP730 |
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LXP730
—
Multi-Rate DSL Framer
24
Datasheet
Transparent and register accessible.
Transparent and OSIO accessible.
Partially Predefined and register accessible.
Partially Predefined and OSIO accessible.
The reset default overhead mode is number 4. The modes are selected by setting bits 7 and 6 of
register 24h, OVRHD_CFG.
In the HWC mode some of the pre-defined bits
’
status is routed to external status pins, i.e.
CRC_ERROR, FEBE, LINK_ACTIVE.
2.12.1
Predefined Overhead
Pre-defined bit-fields support: frame sync word, stuff-bits,
los
,
CRC-6
,
febe
,
indc_r
,
f
bits and user
defined overhead bits. In this mode the user may write to the corresponding bits in the MXOH
registers, but the LXP730 will ignore them and insert the predefined bits into the bit stream.
The frame sync word (FSW) bit pattern consists of the following 14 bits in order from left to right:
(10101000001000), this generates the +3 +3 +3 -3 -3 +3 -3 quat valued sync waveform on the
MDSL. Other valid sync patterns are the time-reversed, sign bit inverted, and the time reversed
sign bit inverted patterns shown in
Table 6
. The generation and detection of the FSW is automatic.
Detection of a frame that has an inverted sign bit causes the MDSL block to invert the sign bits of
the data stream before it is sent to the descrambler.
Stuff-bits are normally either four (4) bits or zero (0) bits immediately before the sync word of the
next frame. The stuffing decision circuit is located in the MDSL Interface block. A special mode
fixes the stuff bits at two per frame for applications that require fixed timing such as connections
from a wireless base station to its remote sites. This is controlled by bit 0 in register 17h,
FIFO_MISC.
The
los
bit is used to notify the other side of the DSL of a loss of source from the PCM bus.
CRC-6
bits are calculated at the transmitter for each frame and sent during the following frame. At
the receiver the CRC-6 is calculated on the received frame, stored and then compared with the
CRC-6 value received in the following frame. Sync word bits, stuff bits and
CRC-6
bits are the
CRC-6 calculation.
The
febe
bit is set in the MX side to the other MDSL unit when a CRC-6 error detected is in the DX
side.
The
indc_r
bit is set in the MX side to notify the other MDSL unit that it is ready to receive
transport data.
2.12.2
Z bits
The first three Z bits in an MDSL frame are reserved for loop ID for multi-loop DSL systems by
the ETSI standard. All other Z bits are user defined. One common use is to send the time slot
configuration from the Local unit to the Remote unit.
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