參數(shù)資料
型號(hào)： LXP730
廠商： Intel Corp.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 26/70頁(yè)
文件大?。?/td> 531K
代理商： LXP730
LXP730
—
Multi-Rate DSL Framer
26
Datasheet
Each data block contains [Z + (N
×
8)] bits. The blocks are transmitted in groups of 12. In T1 mode
Z=1 and the 12 Z-bits per block group are reserved for framing/signalling and are referred to as
f
-
bits. In all other modes they are user accessible overhead bits known as
Z
-bits. The frame structure
matches the 784 kbps structure adopted by T1E1 and ETSI. For N=18 and Z=1, the frame format
follows that of an 1168 kbps HDSL system compliant with ETSI standards.
2.14
Startup Operation
This description applies to the MPC mode for the LXP730. Typically the user sets most of the
desired register values and then sets the RUN bit in register 24h, OVRHD_CFG. At this point the
MX side of the framer is sending data to TDATA and the DX side is looking for the FSW. The next
step requires clearing of INT_STAT register by writing OxFF to it. It must be ensured that the
SK70725/21 chipset is in either Master or Slave mode as needed. The SK70725/21 chipset needs to
be reset and the ACTIVATE bit toggled in the SK70725/21 chipsets. The main control register has
to be toggled. In Master mode, the SK70725/21 will start the activation sequence with the Slave
responding. In a few seconds the data pumps will have set their filter and echo coefficients and
switch to transparent transport mode.
There is an additional setup to consider when the LXP730 is in PCM slave mode and N=18. If
there is no clock running, then there is a halt condition when 18 PCM time slots are selected. The
work around is to temporarily set the last two of the Nx registers to codec configuration, then set
the RUN bit. Once that is done then change the Nx registers back to the desired PCM
configuration.
The DX side of the LXP730 will go to ACTIVE upon receipt of two successive MDSL frames.
When this first occurs, the ACTIVE bit in INT_STAT is set, but will stay reset once it is cleared
until the framer goes to inactive and back to active again. The ACTIVE bit is edge triggered. The
DSLACTIVE bit in CRC_FEBE_ST is level triggered or
‘
sticky
’
.
Once the DSL is active, no support is required to keep it operating. At this point there are basically
two tasks to perform: 1) monitor for error conditions, 2) use the overhead to pass messages/
signalling between the Local and Remote units.
Figure 4. Frame Format for N=12
MDSL Block (784k):
TS1
TS2
TS0
TS4
TS5
TS8
TS7
TS3
TS6
T11
T10
TS9
8
8
8
8
8
8
8
8
8
8
8
8
Z
OH
BLKS 1 - 12
MDSL Frame (784k):
SYNCH
OH
OH
BLKS 13 - 24
OH
BLKS 25 - 36
STUFF
BLKS 37 - 48
6 msec
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