參數(shù)資料
型號: LXP730
廠商: Intel Corp.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 27/70頁
文件大小: 531K
代理商: LXP730
Multi-Rate DSL Framer
LXP730
Datasheet
27
Most of registers/bits can be changed while the RUN bit is set with the following exceptions:
N_MDSL register
TX8KSSEL bit in 17h
The MX and DX FIFOs (MXFIFORXT & DXFIFORXT) should be reset whenever the PCM or
codec clocks are changed while the framer is in the RUN mode. This will cause an interruption in
the payload, but the DSL link will stay up.
2.15
Activation State Machine
The LXP730 framer has an ANSI T1E1.4/94-006 compatible activation state machine. The
operation of the state machine is shown in
Figure 5
.
Figure 5. Activation State Machine
Sync &
RUN/
STOP =
RUN
No
Sync
Initial
"Out-of-Sync"
State 0
ACTIVE = 0
LOS = 1
1
No
Sync
Out
of Sync
State 8
ACTIVE = 0
LOS = 0
9
Sync with No
Change Of
Frame
Alignment
No
Sync
No
Sync
7
6
No
Sync
5
No
Sync
4
No
Sync
3
No
Sync
In
Sync
State 2
ACTIVE = 1
Sync
No
Sync
Sync
Sync
Sync
Sync with Change
Of Frame
Alignment
Sync
COFA = 1
Sync
(COFA = 0)
No
Sync
10 COFA = 1
No
Sync
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