參數(shù)資料
型號(hào): LXP730
廠商: Intel Corp.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 41/70頁(yè)
文件大小: 531K
代理商: LXP730
Multi-Rate DSL Framer
LXP730
Datasheet
41
Figure 19. E1/T1 Input Timing
Table 17. E1/T1 Input Timing Specifications (See Figure 19)
Parameter
Sym
t
SU
t
HT
Min
Typ
1
Max
Unit
Test Conditions
Setup time of T1E1I, FRMIN
30
ns
Referenced from falling edge of PCLK
Hold time of T1E1I, FRMIN
10
ns
Referenced from falling edge of PCLK
E1, T1 clock period
t
PW
488,
647
ns
TCLKI pulse width low
t
PWL
t
PWH
50
ns
TCLKI pulse width high
50
ns
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Figure 20. E1/T1 Output Timing
t
SU
t
PWL
t
PWH
t
HT
TCLKI
T1E1I, FRMIN
t
R
t
F
t
PW
t
D
t
PWH
TCLK0
T1E10,
FRMOUT
t
PWL
t
PW
t
F
t
R
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