參數(shù)資料
型號: LXP730
廠商: Intel Corp.
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 40/70頁
文件大?。?/td> 531K
代理商: LXP730
LXP730
Multi-Rate DSL Framer
40
Datasheet
Figure 17. MDSL Interface Input Timing
Table 15. MDSL Interface Input Timing Specifications (See Figure 17)
Parameter
Sym
t
SU
t
HT
Min
Typ
1
Max
Unit
Test Conditions
Setup time of RDATA
30
ns
Referenced from falling edge of BITCLK
Hold time of RDATA
10
ns
Referenced from falling edge of BITCLK
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Figure 18. MDSL Interface Output Timing
Table 16. MDSL Interface Output Timing Specifications (See Figure 18)
Parameter
Sym
t
D
Min
Typ
1
Max
Unit
Test Conditions
Output delay time of TDATA
100
ns
Referenced from rising edge of BITCLK
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
BITCLK
RDATA
QUATCLK
t
SU
t
HT
Sign bit
Magnitude bit
BITCLK
TDATA
t
D
QUATCLK
Sign bit
Magnitude bit
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