參數(shù)資料
型號: LXP730
廠商: Intel Corp.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 57/70頁
文件大?。?/td> 531K
代理商: LXP730
Multi-Rate DSL Framer
LXP730
Datasheet
57
5.7
Slip Buffer Upper Threshold Register
Address: 19
Abbreviation: SLP_THDH
Read/Write
5.8
Version Register
Address: 1A
Abbreviation: VERSION
Read only
5.9
Internal Clock Control Registers (4 bytes)
5.9.1
ADPLL Control 1
Address: 1B
Abbreviation: PLLCTL1
Read/Write
Table 49. Slip Buffer Upper Threshold
Bit
Name
Default
Description
<7>
SLP_U_EN
0
0 = Use default, 1 = Enable and use Bits <6:0> for the Upper
Threshold. Must be set when Stopped (Run/Stop = 0).
<6:0>
SLP_UPR
0
MPC Mode: Upper Threshold of PCM Receive Slip Buffer (Default
32+N). HWC Mode: Not Used.
Table 50. Version
Bit
Name
Default
Description
<7:0>
VER
0
Version of Device.
Table 51. ADPLL Control 1
Bit
Name
Default
Description
<7:0>
CFREQ(17:1
0)
40
Center Frequency of the ADPLL.
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