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參數(shù)資料
| 型號： | LXP730 |
| 廠商： | Intel Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 61/70頁 |
| 文件大?。?/td> | 531K |
| 代理商： | LXP730 |
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Multi-Rate DSL Framer
—
LXP730
Datasheet
61
5.13.2
Overhead Configuration
Address: 24
Abbreviation: OVRHD_CFG
Read/Write
5.13.3
CRC Error Counter
Address: 25
Abbreviation: CRC_ERR_CNT
Read/Write
4
GAP_CLK
0
Gapped DSL Clock Out Select, Enable output for gapped receive
DSL clock. 0 = output always high, 1 = Gapped clock out.
3
Z_CTL
0
Z bit Mux control, 1 = Z bits to registers (Z_NUM = 0 only), 0 = Z bits
to OSIO.
2
ASPSEL
0
ADPI serial port select enable. 0 = disabled, 1 = enabled. Enabling
the ADPI disables codec frame syncs 7, 8, 9, and 10.
1
CCLK_OE
0
Codec Clock Output Enable. 0 = disabled, 1 = enabled.
0
PCM_FS_PO
S
1
PCM Frame Sync Position: 0 = first bit of the frame, 1= last bit of the
frame.
Table 58. Miscellaneous Control (Continued)
Bit
Name
Default
Description
Table 59. Overhead Configuration
Bit
Name
Default
Description
7
Par/Ser
0
Overhead Data Mode: set to
‘
0
’
for external pins,
‘
1
’
for internal
register.
6
Trans/PreDef
0
‘
1
’
for transparent mode,
‘
0
’
for limited pre-defined mode.
5
CRC_CNT
0
CRC-6 error counter mode:
‘
0
’
for reset when read,
‘
1
’
for modulo
count.
4
FEBE_CNT
0
FEBE error counter mode:
‘
0
’
for reset when read,
‘
1
’
for modulo
count.
3
L/R
0
Local/Remote Mode,
‘
0
’
for Remote,
‘
1
’
for Local, selects scrambling
polynomial.
2
SRC_EN
0
Scrambler Enable,
‘
0
’
enabled,
‘
1
’
disabled.
1
DSL_LB
0
DSL Interface Loop Back,
‘
0
’
disabled,
‘
1
’
enabled.
0
RUN/STOP
0
0 = Set MDSL framer state machine to Deactivated state, 1 = Set
MDSL framer state machine to Activation state.
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