參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 13/71頁(yè)
文件大小： 906K
代理商： MC145225
MC145225 MC145230
13
MOTOROLA RF/IF DEVICE DATA
When the Mode pin is high, these pins are digital inputs
Pol and Pol which control the polarity of the phase/frequency
detectors. See Tables 7 and 8. Positive polarity is used when
an increase in an external VCO control voltage input causes
an increase in VCO output frequency. Negative polarity is
used when a decrease in an external VCO control voltage
input causes an increase in VCO output frequency.
Table 7. Main Phase/Frequency Detector Polarity
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(PDout–Lo and PDout–Hi)
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High
High
Negative
Table 8. Secondary Phase/Frequency
Detector Polarity
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Mode Pin
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(PDout)
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5B. REFERENCE PINS
Osce and Oscb
Pins 1 and 32 — Reference Oscillator Transistor Emitter
and Base
These pins can be configured to support an external
crystal in a Colpitts oscillator configuration. The required
connections for the crystal circuit are shown in the
Crystal
Oscillator Considerations
section.
Additionally, the pins can be configured to accept an
external reference frequency source, such as a TCXO. In this
case, the reference signal is ac coupled into Osce and the
Oscb pin is left floating. See Figure 11.
Bit C6 and the Mode input pin control the configuration of
these pins per Table 9.
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Low
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Pin
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Bit C6
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Configuration
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Supports Crystal
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Comment
C6 used to control
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5C. LOOP PINS
fin and fin
Pins 12 and 13 — Frequency Input for Main Loop (PLL)
These pins feed the on–chip RF amplifier which drives the
high–speed N counter. This input may be fed differentially.
However, it is usually used in a single–ended configuration
with fin driven while fin is tied to a good RF ground (via a
capacitor). The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the fin input is specified as a level across a 50
load driven by a 50
source. A VCO that can drive a load
within the data sheet limits can also drive fin. Usually, to avoid
load pull and resultant frequency modulation of the VCO, fin is
lightly coupled by a small value capacitor and/or a resistor.
See the applications circuit of Figure 65.
fin
Pin 30 — Frequency Input for Secondary Loop (PLL )
This pin feeds the on–chip RF amplifier which drives the
high–speed N counter. This input is used in a single–ended
configuration. The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the fin input is specified as a level across a
50
load driven by a 50
source. A VCO that can drive a
load within the data sheet limits can also drive fin. Usually, to
avoid load pull and resultant frequency modulation of the
VCO, fin is lightly coupled by a small value capacitor and/or
a resistor. See the applications circuit of Figure 65.
If the secondary loop is not used, PLL should be placed in
standby and fin should be left open.
PDout–Hi and PDout–Lo
Pins 19 and 20 — Phase/Frequency Detector Outputs
for Main Loop (PLL)
Each pin is a three–state current source/sink/float output
for use as a loop error signal when combined with an external
low–pass loop filter. Under bit control, PDout–Lo has either
one–quarter or one–eighth the output current of PDout–Hi per
Table 10. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 20.
Table 10. Current Ratio of PDout–Hi
PDout–Hi:PDout–Lo
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When the Mode pin is high, positive polarity occurs when
the Pol pin is low. Also, when the Mode pin is low, polarity
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