參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 65/71頁(yè)
文件大?。?/td> 906K
代理商： MC145225
MC145225 MC145230
65
MOTOROLA RF/IF DEVICE DATA
8B. INITIALIZING THE DEVICE
Introduction
The registers retain data as long as power is applied to the
device. The R and N registers contain counter divide ratios
for the main loop, PLL. The R and N registers contain
counter divide ratios for the secondary loop, PLL . Additional
control bits are located in the R , N, and C registers. The D
register controls the DACs. Section 8A is a handy reference
for register access and bit definitions.
The C, D, R , and N registers can be directly written, and
have an immediate impact on chip operation. The Hr and Hn
registers can be directly written, but have no immediate
impact on chip operation. This is because the Hr and Hn
registers are the front–ends of double buffers. The Hr register
feeds the R register. The Hn register feeds the N register.
Changing data in the R and/or N registers is done with a
write to the Hr and/or Hn register, respectively, followed by a
write to the N register. The transfer of data from the Hr to R
and Hn to N registers is triggered with a write to the N
register.
Typically, the Hr and Hn registers are written once, during
initialization after power up. The Hr and Hn registers only
need to be accessed if their data is changing.
An Example
Following is an initialization example for a system with a
main loop that covers 1.8 to 2.1 GHz in 30 kHz steps. An
external reference of 19.44 MHz is utilized. The secondary
loop is selected to run at 200 MHz. Both VCOs are positive
polarity meaning that when the input control voltage
increases, the output frequency increases. A divided–down
reference is not needed (fout and fout). Therefore, the Mode
pin is tied to Vpos and the Pol and Pol pins are tied to ground.
The following initialization gives serial data examples for
BitGrabber access of the C, Hr, and N registers.
Initialization
Below is the six–step initialization sequence used after
power up for the example given above.
Programming the C register first is recommended if the
voltage multiplier is utilized. There are three important criteria
to note. Violation of any criterion may cause the voltage
multiplier to collapse. The first criterion is that after power up,
a sufficient time interval must be provided (after the C and R
registers are initialized) for the on–chip voltage multiplier to
build up the voltage on the Cmult pin. This interval is
determined by the external capacitor size tied to the Cmult pin
and the charging current which is about 100
μ
A. After this
interval, the chip can maintain the voltage on the Cmult pin
and the phase/frequency detectors for the main loop may be
safely activated. The second criterion is that before the
phase/frequency detectors are activated, legitimate divide
ratios (pertinent to the application) must be loaded in the
registers. The third criterion is a hardware issue. The three
criteria are discussed with more detail in Section 7E.
If the voltage multiplier is not used, Step 1 is eliminated
and the initialization sequence starts with Step 2.
Step 1: Load the C Register
The C register is programmed such that the main loop’s
phase/frequency detector outputs are floating (PD Float bit
C4 = 1), the reference circuit is active (Osc Stby bit C2 = 0),
and an external reference is accommodated (Out B/Xref bit
C6 = 1, with the Mode pin high). When the voltage multiplier
is enabled by programming the R register, the voltage is
allowed to build on the Cmult pin such that a voltage higher
than the main supply voltage is providing power to the
phase/frequency detectors. Both loops are active (PLL Stby
bits C1 = C0 = 0). Also, for this example, Output A and Output
C are programmed low (Out bits C7 = C5 = 0).
In summary, hexadecimal 58 or $58 is serially transferred
(BitGrabber access with no address bits).
Step 2: Load the R Register
For the secondary loop, the 19.44 MHz reference is
divided down to 80 kHz by the R counter; the divide ratio is
243. Per Section 8A, the value is doubled to 486. The 16
LSBs of the R register determine the R counter divide ratio.
Therefore, 486 is converted to $01E6 and becomes the 16
LSBs (R 15 to R 0) in the R register. Test/Rst bit R 16 must
be a 0. Bits R 19 to R 17 determine the refresh rate of the
voltage multiplier. The frequency at Osce is <20 MHz.
Therefore, per Section 8A, bits R 19 to R 17 must be 001. If
Output A is needed as a MCU port expander, bits R 21 =
R 20 = 0. Per Section 8A, Y Coefficient bits R 23 R 22 = 10.
In summary, $058201E6 is serially transferred
(conventional access with an address of 0101).
Step 3: Load the Hr Register
For the main loop, the 19.44 MHz reference must be
divided down to 30 kHz by the R counter; the divide ratio is
648. Per Section 8A, the ratio 648 is doubled to 1296 and
then converted to $510. The Hr register value is programmed
as $0510. When the Hr register contents are transferred to
the R register, the R counter divide ratio is determined.
In summary, $0510 is serially transferred (BitGrabber
access). This value is transferred from the Hr to the R
register when the N register is accessed in Step 5.
Step 4: Load the Hn Register
For the secondary loop, the phase detector is chosen to
run at 80 kHz. Therefore, 80 kHz must be multiplied up to
200 MHz which is a factor of 2500. The factor is converted to
$9C4. The Hn register is programmed as $09C4. When the
Hn register contents are transferred to the N register, the N
counter divide ratio is determined.
In summary, $040009C4 is serially transferred
(conventional access with an address of 0100). The value
$09C4 is transferred to the N register when the N register is
accessed in Step 5.
Step 5: Load the N Register
For this example, the IC is initialized to tune the lowest end
of the main loop. The lowest end of the main loop’s frequency
range is 1.8 GHz. Therefore, the 30 kHz must be multiplied
up to 1.8 GHz which is a factor of 60,000 or $EA60 to be
loaded into bits N17 to N0 of the N register. Bit N18 is
programmed to 0 for a PDout–Hi to PDout–Lo current ratio of
4:1. If PDout–Lo is used for the main loop, bits N21 to N19
must be 001. (PDout–Lo must be used to initialize the device
when adaptis used, see Section 8D.) Bit N22 = 0 to select a
lock detect window of approximately 32 / Osce =
32/19.44 MHz or 1.6
μ
s. Bit N23 must be programmed to 1
by the user. (When the Mode pin is high, programming N23 to
a 0 is for Motorola use only.)
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