參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 63/71頁(yè)
文件大小： 906K
代理商： MC145225
MC145225 MC145230
63
MOTOROLA RF/IF DEVICE DATA
A3
A2
A1
A0
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
0
Hn
′
REGISTER
1
0
0
x
x
x
x
MSB of N
′
Counter
Divide Value
8A.
QUICK REFERENCE (continued)
N
′
15
. . .
N
′
12
N
′
11
. . .
N
′
8
N
′
7
. . .
N
′
4
N
′
3
. . .
N
′
0
Address Nibble
EXAMPLE:
To program the N
′
counter to divide by 1000 in decimal, first convert 1000 to hexadecimal: $3E8. Then, add leading 0s
(if necessary) to form 2 bytes (4 nibbles): $03E8. Finally, configure address bits A3 to A0 and load the Hn
′
register.
When the N register is subsequently loaded, data passes from the first Hn
′
register (buffer) to the second N
′
register
(buffer). (Data is still retained in the Hn
′
register.)
x
x
x
x
x
x
x
x
LSB of N
′
Counter
Divide Value
Conventional Access only
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