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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 60/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
60
MOTOROLA RF/IF DEVICE DATA
Hr REGISTER
8A. QUICK REFERENCE (continued)
Most Significant
Nibble
(Shifted in First)
MSB of R Counter
Divide Value
Least Significant
Nibble
(Shifted in Last)
LSB of R Counter
Divide Value
EXAMPLE:
To program the R counter to divide by 1000 in decimal, first multiply 1000 by 2 which is 2000. Convert 2000 to
hexadecimal: $7D0. Then, add leading 0s to form 2 bytes (4 nibbles): $07D0. Finally, load the Hr register bits R15
to R0 with $07D0. When the N register is subsequently loaded, data passes from the first Hr register (buffer) to the
second R register (buffer). (Data is still retained in the Hr register.)
With BitGrabber, no address bits are needed. With a conventional load, address bits A3 to A0 must be included.
NOTE:
Hexadecimal numbers are preceded with a dollar sign. For example: hexadecimal 1234 is shown as $1234.
LSB of R Counter
Divide Value
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
0
Conventional Access
0
0
1
Address Nibble
MSB of R Counter
Divide Value
BitGrabber Access
R7
. . .
R4
R3
. . .
R0
R11
. . .
R8
R15
. . .
R12
R7
. . .
R4
R3
. . .
R0
R15
. . .
R12
R11
. . .
R8
A3
A2
A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
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