參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 17/71頁(yè)
文件大?。?/td> 906K
代理商： MC145225
MC145225 MC145230
17
MOTOROLA RF/IF DEVICE DATA
C REGISTER BITS
See Figure 13 for C register access and serial data
formats.
Out A (C7)
When the Output A pin is selected as a General–Purpose
Output (via bits R 21 = R 20 = 0), bit C7 determines the state
of the pin. When C7 is 1, Output A is forced to a high level.
When C0 is 0 Output A is forced low.
When Output A is not selected as a General–Purpose
Output, bit C7 has no function; i.e., C7 is a “don’t care” bit.
Out B/XRef (C6)
Bit C6 is a dual–purpose bit.
When the Mode pin is tied low, C6 and C1 (PLL Stby), can
be used to control Output B. See Table 12. (The reference
circuit defaults to crystal configuration.)
When the Mode pin is tied high, additional control of the
reference circuit is allowed. See Table 13.
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Out C (C5)
This bit determines the state of the Output C pin. When C5
is 1, Output C is forced to a high–impedance state. When C5
is 0, Output C is forced low.
PD Float (C4)
This bit controls the phase detector for the main loop,
outputs PDout–Hi and PDout–Lo. When this bit is 0, the main
phase detector operates normally. When the bit is 1, the
outputs are forced to the floating state which opens the loop
and allows modulation to be introduced into the external VCO
input. During this time, the counters are still active. This bit is
inhibited from affecting the phase detector during a PDout–Hi
or PDout–Lo pulse.
If the loop is locked prior to C4 being set to 1, the lock
detect signal from the main loop continues to indicate “l(fā)ock”
immediately after PD Float is set to 1. If the phase of the loop
drifts outside the lock detect window, then the lock detect
signal indicates “not locked”. If the loop is not locked, and PD
Float is set to 1, then the lock detect signal from the main loop
continues to indicate “not locked”.
PD Float (C3)
This bit controls the phase/frequency detector for the
secondary loop, output PDout. When this bit is 0, the
secondary phase detector operates normally. When the bit is
1, the output is forced to the floating state which opens the
loop and allows modulation to be introduced into the external
VCO input. During this time, the counters are still active. This
bit is inhibited from affecting the phase detector during a
PDout pulse.
If the loop is locked prior to C3 being set to 1, the lock
detect signal from the secondary loop continues to indicate
“l(fā)ock” immediately after PD Float is set to 1. If the phase of
the loop drifts outside the lock detect window, then the lock
detect signal indicates “not locked”. If the loop is not locked,
and PD Float is set to 1, then the lock detect signal from the
secondary loop continues to indicate “not locked”.
Osc Stby (C2)
This bit controls the crystal oscillator and external
reference input circuit. When this bit is 0, the circuit is active.
When the bit is 1, the circuit is shut down and is in the
low–power standby mode. When this circuit is shut down, a
keep–alive oscillator for the voltage doubler is activated,
unless the doubler is shut off via bits in the R register. In the
crystal oscillator mode, when C2 transitions from a 1 to a 0
state, a kick–start circuit is engaged for a few milliseconds.
The kick–start circuit ensures self–starting for a
properly–designed crystal oscillator
NOTE
Whenever C2 is 1, both bits C1 and C0 must be
1, also.
To minimize standby supply current, the voltage multiplier
may be shut down (by bits R 19, R 18, and R 17 being all
zeroes). If this is the case and the voltage multiplier feature is
being used, the user must allow sufficient time for the
phase/frequency detector supply voltage to pump up when
the multiplier is brought out of standby. This “pump up” time is
dependent on the Cmult capacitor size. Pump current is
approximately 100
μ
A. During the pump up time, either the
PLL standby bits C1 and C2 must be 1 or the phase/
frequency detector float bits C3 and C4 must be 1.
PLL Stby (C1)
When set to 1, this bit places the main PLL in the standby
mode for reduced power consumption. PDout–Hi and
PDout–Lo are forced to the floating state, the N and R
counters are inhibited from counting, the main loop’s input
amp is shut off, the Rx current is inhibited, and the main
phase/frequency detector is shut off. The reference oscillator
circuit is still active and independently controlled by bit C2.
When this bit is programmed to 0, the main PLL is taken
out of standby in two steps. First, the input amplifier is
activated, all counters are enabled, and the Rx current is no
longer inhibited. Any fR and fV signals are inhibited from
toggling the phase/frequency detectors and lock detector at
this time. Second, when the fR pulse occurs, the N counter is
loaded, and the phase/frequency and lock detectors are
initialized via both flip–flops being reset. Immediately after
the load, the N and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase
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