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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 62/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
62
MOTOROLA RF/IF DEVICE DATA
Don’t Care
Nibble
(Shifted in First)
0
R
′
REGISTER
1
0
1
Y
Coefficient
Output A
Function
Test/Rst
MSB of R
′
Counter Divide
Value
V–Mult
Control
Least
Significant Nibble
(Shifted in Last)
8A.
QUICK REFERENCE (continued)
Address Nibble
Y Coefficient
0 0 = Maximum frequency on fin
≤
550 MHz
0 1 = Maximum frequency on fin
≤
1.2 GHz
1 0 = Maximum frequency on fin
≤
2.2 GHz
1 1 = Not used
Output A Function = Controls Output A Mux
0 0 = General–Purpose Output
0 1 = fR
1 0 = fR
′
1 1 = Phase Detector pulse
V–Mult Control = Voltage Multiplier Control
0 0 0 = Multiplier OFF, 9 MHz
≤
Osce
≤
80 MHz
0 0 1 = Multiplier ON, 9 MHz
≤
Osce
≤
20 MHz
0 1 0 = Multiplier ON, 20 MHz < Osce
≤
40 MHz
0 1 1 = Multiplier ON, 40 MHz < Osce
≤
80 MHz
Test/Rst = Test/Reset
0 = only programming value allowed
LSB of R
′
Counter
Divide Value
EXAMPLE:
When the Mode pin is tied low, see Table 21 for R
′
counter programming. When the Mode pin is tied high, to program the
R
′
counter to divide by 1000 in decimal, first multiply 1000 by 2, which is 2000. Convert 2000 to hexadecimal: $7D0. Then,
add leading 0s to form 2 bytes (4 nibbles); this becomes bits R
′
15 to R
′
0. Bits R
′
23 to R
′
16 should be appropriate to control
the above functions. Finally, load the R
′
register.
With a conventional load, address bits A3 to A0 must be included.
NOTE:
Hexadecimal numbers are preceded with a dollar sign. For example: hexadecimal 1234 is shown as $1234.
R
′
23 R
′
22R
′
21R
′
20
R
′
19 R
′
18R
′
17R
′
16
R
′
15
. . .
R
′
12
R
′
11
. . .
R
′
8
R
′
7
. . .
R
′
4
R
′
3
. . .
R
′
0
A3
A2
A1
A0
x
x
x
x
Conventional Access only
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