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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 67/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
67
MOTOROLA RF/IF DEVICE DATA
shift time shown in Figure 64. Included in the first data set are
N23 = 1 which is required when the Mode pin is high, N22 = 0
for the lock detect window of 1.6
μ
s, and N18 = 0 for a current
ratio of 4:1 (because the phase detector is running at
approximately 4x the step size). Note that bits N23, N22, and
N18 are unchanged from the initialization values.
For the second data set, bits N23, N22, and N18 are
unchanged. Bits N21, N20, and N19 must be programmed as
001. This enables PDout–Lo for the exact tune after time out.
In summary, two data sets need to be sent to the device:
{R1, N1} and {R2, N2}. They are sent in succession as R1,
N1, R2, N2; where R1 is the R register value for the first data
set, N1 is the N register value for the first set, etc. For the
example, these values are {R1, N1} = {$0115, $A8321A} and
{R2, N2} = {$0510, $88EA69}. See Figure 64.
Tuning Other Channels
Tuning other channels for the main loop, while keeping the
secondary loop at a constant frequency, requires sending
two data sets to the part {R1, N1} and {R2, N2}. See Table 23.
8E. CONTROLLING THE DACs
Introduction
The two 8–bit DACs are independent circuit blocks on the
chip. They have no interaction with other circuits on the chip.
A single 16–bit register, called the D register, holds the binary
value which controls both DACs.
Programming the DACs
A DAC programmed for 0 scale is in the low–power mode.
The 0 scale is programmed as $00 for each 8–bit DAC.
As an example, consider a system that uses just one of the
DACs (DAC 1). The other DAC output is unused and is
programmed for 0 output. If a condition for a system requires
that the DAC have a half–scale output, then DAC 1 is
programmed as $80.
In summary, $03000080 is serially transferred
(conventional access with an address of 0011).
Table 23. Main Loop Tuning Using Horseshoe With Adapt
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Target
Approximate Tuning
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