Signal Description
2-8
MC68307 USER’S MANUAL
MOTOROLA
2.3.2 Address Strobe (AS)
This three-state active-low output signal indicates that there is a valid address on the
address bus during M68000 bus cycles. It should be ignored during 8051-compatible bus
cycles as the eight low-order address lines also carry the data bus during such a cycle. Dur-
ing all types of bus cycle, it should be taken into account when other bus masters are arbi-
trating for the bus, as it indicates that the MC68307 is still using the bus.
When the bus is arbitrated to an external master, or during reset, AS is three-stated.
2.3.3 Read/Write (R/W)
This three-state output signal defines the data-bus transfer as a read or a write cycle. The
R/W signal relates to the data strobe signals described in the following paragraphs. When
the R/W line is high, the processor reads from the data bus. When the R/W line is low, the
processor drives the data bus. The processor also drives the data bus during a read from
an internal location, to aid emulation and debug.
When the bus is arbitrated to an external master, or during reset, R/W is three-stated.
2.3.4 Data Strobes, Upper and Lower (UDS, LDS)
These three-state active-low output signals control the flow of data on the M68000 data bus.
Table 2-10 lists the combinations of these signals and the corresponding data on the bus in
16-bit wide mode.
In 8-bit wide bus mode (programmed in conjunction with chip selects), all bus cycles appear
as 8-bit reads or writes to the upper half of the data bus (D15–D8), and so UDS only is
asserted. A0 should be used to determine even or odd byte being addressed in this case; it
is valid whenever the external AS signal is asserted during such a cycle. There is no external
indication of data-bus width other than the chip-select asserted. The user has the knowledge
of what bus width that chip-select is programmed to provide, for any given configuration of
the MC68307 in a system.
Table 2-10. Data Strobe Control of Data Bus
UDS
LDS
R/W
D15–D8
D7–D0
High
—
No Valid Data
Low
High
Valid Data Bits 15–8
Valid Data Bits 7–0
High
Low
High
No Valid Data
Valid Data Bits 7–0
Low
High
Valid Data Bus 15–8
No Valid Data
Low
Valid Data Bits 15–8
Valid Data Bits 7–0
High
Low
Valid Data Bits 7–0
Low
High
Low
Valid Data Bits 15–8