System Integration Module
5-40
MC68307 USER’S MANUAL
MOTOROLA
Interrupt Priority Level Timer 1, Timer 2, UART, MBUS, T1IPL2–0, T2IPL2–0, MBIPL2–0,
UAIPL2–0
These bits allow the user to specify the IPL for the corresponding on-chip peripheral mod-
ule interrupt input line (Timer 1, Timer 2, UART and M-bus respectively). When an inter-
rupt occurs, the interrupt controller logic asserts the correct priority code on the EC000
interrupt level inputs, and respond to the subsequent acknowledge cycle by coordinating
the return of the appropriate vector, as programmed into the programmable interrupt vec-
tor register or UART interrupt vector register.
000 =
The corresponding interrupt source is inhibited and cannot generate inter-
rupts.
001 - 111 =The corresponding interrupt source is enabled, and can generate an inter-
rupt to the EC000 core processor with the indicated priority level.
The remaining four bits (Bits 14, 11, 7, 3) are reserved for future implementation, and
should always be written as one. When read, their value should be ignored.
5.2.4.3 PROGRAMMABLE INTERRUPT VECTOR REGISTER (PIVR). This register spec-
ifies the vector numbers which is returned by the interrupt controller in response to Interrupt
Acknowledge cycles for the various peripherals and discrete interrupt sources. The high four
bits of the vector number are programmed in the PIVR, and the low four bits are provided
by the interrupt controller depending on the highest priority source which is currently active
for the specific IPL being responded to in the current acknowledge cycle.
IV7–IV4—Interrupt Vector Numbers 7–4
These bits provide the high four bits of the interrupt vector for interrupt acknowledge cy-
cles from all sources except the UART, which provides its own, unique vector number.
The UART has a separate vector register for historical reasons, due to its compatibility
with the MC68681 DUART.
Bits 3–0—Unused
These bits are ignored on a write cycle, and return 1 on a read cycle. The interrupt con-
troller provides the appropriate encoding on these four bits of the vector (Refer to Section After cold reset, this register contains the value $0F, although no interrupts are ever
propagated to the CPU until the PIVR is first programmed (not even level 7 interrupts). Only
write to the PIVR after the CPU stack pointer has been set up to point to valid addressable
RAM, i.e., after the chip selects for RAM have been set up.
PIVR
MBASE+$027
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
—
RESET:
0
1
Read/Write
Supervisor or User