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參數(shù)資料
| 型號(hào)： | MC68307PU16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 82/264頁 |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307PU16 |
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Serial Module
8-12
MC68307 USER’S MANUAL
MOTOROLA
8.3.4 Multidrop Mode
The UART can be programmed to operate in a wakeup mode for multidrop or multiprocessor
applications. Functional timing information for the multidrop mode is shown in Figure 8-8.
The mode is selected by setting bits 3 and 4 in mode register 1 (UMR1). This mode of oper-
ation allows the master station to be connected to several slave stations (maximum of 256).
In this mode, the master transmits an address character followed by a block of data charac-
ters targeted for one of the slave stations. The slave stations have their channel receivers
disabled. However, they continuously monitor the data stream sent out by the master sta-
tion. When an address character is sent by the master, the slave receiver channel notifies
its respective CPU by setting the RxRDY bit in the USR and generating an interrupt (if pro-
grammed to do so). Each slave station CPU then compares the received address to its sta-
tion address and enables its receiver if it wishes to receive the subsequent data characters
or block of data from the master station. Slave stations not addressed continue to monitor
the data stream for the next address character. Data fields in the data stream are separated
by an address character. After a slave receives a block of data, the slave station's CPU dis-
ables the receiver and initiates the process again.
A transmitted character from the master station consists of a start bit, a programmed number
of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. The A/
D bit identifies the type of character being transmitted to the slave station. The character is
interpreted as an address character if the A/D bit is set or as a data character if the A/D bit
is cleared. The polarity of the A/D bit is selected by programming bit 2 of UMR1. UMR1
should be programmed before enabling the transmitter and loading the corresponding data
bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless
of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and
loads the character into the receiver holding register FIFO stack provided the received A/D
bit is a one (address tag). The character is discarded if the received A/D bit is a zero (data
tag). If the receiver is enabled, all received characters are transferred to the CPU via the
receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is
loaded into the status portion of the stack normally used for a parity error (USR bit 5). Fram-
ing error, overrun error, and break detection operate normally. The A/D bit takes the place
of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode
may still contain error detection and correction information. One way to provide error detec-
tion, if 8-bit characters are not required, is to use software to calculate parity and append it
to the 5-, 6-, or 7-bit character.
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相關(guān)代理商/技術(shù)參數(shù) |
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