EC000 Core Processor
MOTOROLA
MC68307 USER’S MANUAL
4-15
An interrupt request is made to the processor by encoding the interrupt request level on the
IPL2–IPL0; a zero indicates no interrupt request. Interrupt requests arriving at the processor
do not force immediate exception processing, but the requests are made pending. Pending
interrupts are detected between instruction executions. If the priority of the pending interrupt
is lower than or equal to the current processor priority, execution continues with the next
instruction, and the interrupt exception processing is postponed until the priority of the pend-
ing interrupt becomes greater than the current processor priority.
If the priority of the pending interrupt is greater than the current processor priority, the excep-
tion processing sequence is started. A copy of the status register is saved; the privilege
mode is set to supervisor mode; tracing is suppressed; and the processor priority level is set
to the level of the interrupt being acknowledged. The processor fetches the vector number
from the interrupting device by executing an interrupt acknowledge cycle, which displays the
level number of the interrupt being acknowledged on the address bus. If external logic
requests an automatic vector, the processor internally generates a vector number corre-
sponding to the interrupt level number. If external logic indicates a bus error, the interrupt is
considered spurious, and the generated vector number references the spurious interrupt
vector. The processor then proceeds with the usual exception processing. The saved value
of the program counter is the address of the instruction that would have been executed had
the interrupt not been taken. The appropriate interrupt vector is fetched and loaded into the
program counter, and normal instruction execution commences in the interrupt handling rou-
tine.
4.6.3 Uninitialized Interrupt Exception
NOTE
The uninitialized interrupt vector of the EC000 core is never
used in the MC68307, but is described here for completeness;
the MC68307 handles all interrupt conditions separately in the
interrupt controller (see Section 5.1.4 Interrupt Processing).
An interrupting device provides a EC000 core interrupt vector number and asserts data
transfer acknowledge (DTACK) or bus error (BERR) during an interrupt acknowledge cycle
by the EC000 core. If the vector register has not been initialized, the responding M68000
family peripheral provides vector number 15, the uninitialized interrupt vector. This response
conforms to a uniform way to recover from a programming error.
4.6.4 Spurious Interrupt Exception
NOTE
The spurious interrupt vector of the EC000 core is never used in
the MC68307, but is described here for completeness; the
MC68307 handles all interrupt conditions separately in the inter-
rupt controller (see Section 5.1.4 Interrupt Processing).
During the interrupt acknowledge cycle, if no device responds by asserting DTACK, BERR
should be asserted to terminate the vector acquisition. The processor separates the pro-
cessing of this error from bus error by forming a short format exception stack and fetching