System Integration Module
5-24
MC68307 USER’S MANUAL
MOTOROLA
NOTE
Regardless of the state of the chip select programming, this bit
is not set and BERR is not asserted for an address decode con-
flict occurring during access to a SCR. This is provided to guar-
antee access to the system configuration registers (MBAR and
SCR) during initialization.
WPV—Write-Protect Violation
This bit is set when the EC000 core processor attempts to write to a location that has the
RW bit set to zero (read only) in its associated chip select base register. Provided the
WPVE bit is set, BERR is asserted on the bus cycle that sets this bit. If WPV and WPVE
are both set when a second write protect violation occurs, BERR is still generated. The
chip select is not asserted.
Write a one to this location to clear the status bit. Writing a zero has no effect.
HWT—Hardware Watchdog Timeout
This status bit is set during a bus error (BERR asserted) caused by the hardware watch-
dog timeout reaching its timeout period without a DTACK being received or generated in-
ternally. Note that the bus error occurs even if this status bit is already set.
Write a one to this location to clear the status bit. Writing a zero has no effect.
RS1–RS0 — Reset Source Indication
These bits record the source of the most recent reset condition or wakeup from sleep
mode (not including a peripheral reset initiated by the processor running a RESET instruc-
tion). Writing to these bits has no effect on their set value. The valid combinations are as
follows (RS1 first, then RS0):
00 = Cold reset (power-on)
01 = Cold reset (reset/halt input signals)
10 = Warm reset (software watchdog timeout)
11 = Wakeup from low-power sleep mode (no reset involved)
Bits 28, 25 and 24—Reserved by Motorola
These status bits are as yet undefined, and may be used for Motorola internal test or for
future options. As such they may at times have a 1 or a 0 value. Do not rely on them being
always zero when performing comparisons.