EC000 Core Processor
4-14
MC68307 USER’S MANUAL
MOTOROLA
4.6.1 Reset Exception
The reset exception corresponds to the highest exception level. The processing of the reset
exception is performed for system initiation and recovery from catastrophic failure. Any pro-
cessing in progress at the time of the reset is aborted and cannot be recovered. The proces-
sor is forced into the supervisor state, and the trace state is forced off. The interrupt priority
mask is set at level 7. The vector number is internally generated to reference the reset
exception vector at location 0 in the supervisor program space. Because no assumptions
can be made about the validity of register contents, in particular the SSP, neither the pro-
gram counter nor the status register are saved. The address in the first two words of the
reset exception vector is fetched as the initial SSP, and the address in the last two words of
the reset exception vector is fetched as the initial program counter. Finally, instruction exe-
cution is started at the address in the program counter. The initial program counter should
point to the power-up/restart code.
The RESET instruction does not cause a reset exception; it asserts the RESET signal to
reset external devices, which allows the software to reset the system to a known state and
continue processing with the next instruction.
4.6.2 Interrupt Exceptions
NOTE
In the MC68307, all external and internal interrupt requests are
controlled by the interrupt controller. The interrupt controller is
always the interrupting device to the EC000 core, supplying the
appropriate interrupt request level to the EC000 core via the
internal IPL2–IPL0 lines. When the EC000 core performs an
interrupt acknowledge, the interrupt controller provides the
corresponding vector on the data bus and terminates the access
with a DTACK. This section considers the interrupt processing
from the perspective of the EC000 core. It is worth noting that,
from the MC68307’s perspective, the EC000 IPL2–IPL0 lines
are internal, and also the EC000 autovectoring is not supported,
but is instead handled separately by the interrupt controller.
Refer to Section 5.1.4 Interrupt Processing for further
information on the interrupt operation.
Seven levels of interrupt priorities are provided, numbered from 1–7. Level 7 has the highest
priority. Devices can be chained externally within interrupt priority levels, allowing an unlim-
ited number of peripheral devices to interrupt the processor. The status register contains a
3-bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority
levels less than or equal to the current priority. Priority level 7 is a special case. Level 7 inter-
rupts cannot be inhibited by the interrupt priority mask, thus providing a non-maskable inter-
rupt capability. An interrupt is generated each time the interrupt request level changes from
some lower level to level 7. A level 7 interrupt may still be caused by the level comparison
if the request level is a 7 and the processor priority is set to a lower level by an instruction.