Signal Description
MOTOROLA
MC68307 USER’S MANUAL
2-11
crystal is used it should be in the range 1 MHz to 16.67 MHz. When an external clock is
used, it must provide a CMOS level at the required system clock frequency.
2.5.2 Clock Output (CLKOUT)
This output clock signal is derived from the on-chip clock oscillator. This clock is used by the
processor and the internal peripherals. All MC68307 bus timings are referenced to the CLK-
OUT signal rather than the EXTAL input signal, as there is a skew between the two. The
clock output is active from reset, but can be turned off by the software writing to the system
control register, in order to save power or control external devices.
2.6 TEST SIGNALS
The following signals are used with the on-board test logic defined by the IEEE 1149.1 stan-
dard. Refer to Section 9 IEEE 1149.1 Test Access Port for more information on the use of
these signals.
2.6.1 Test Clock (TCK)
This input provides a clock for on-board test logic defined by the IEEE1149.1 standard.
2.6.2 Test Mode Select (TMS)
This input controls test mode operations for on-board test logic defined by the IEEE 1149.1
standard. Connecting TMS to VCC disables the test controller, making all JTAG circuits
transparent to the system.
2.6.3 Test Data In (TDI)
This input is used for serial test instructions and test data for on-board test logic defined by
the IEEE 1149.1 standard.
2.6.4 Test Data Out (TDO)
This output is used for serial test instructions and test data for on-chip test logic defined by
the IEEE 1149.1 standard.
2.7 M-BUS I/O SIGNALS
The M-bus is an I2C-bus-compatible serial interface on two wires. All devices connected to
the bus must have open-drain or open-collector outputs. The logical AND function is exer-
cised on both lines with pullup resistors being required. The pins are multiplexed with port
B, individual pin function being programmable. Port B bits 0 and 1 are therefore always
open-drain input/outputs. Refer to Section 7 M-Bus Interface Module for more information
on these signals.
2.7.1 Serial Clock (SCL/PB0)
This bidirectional open-drain signal is the clock signal for the M-bus interface. Either it is
driven by the M-bus module when the bus is in the master mode or it becomes the clock
input when the M-bus is in the slave mode. When programmed as general-purpose input/
output, this signal functions as bit 0 of port B.