Dual Timer Module
MOTOROLA
MC68307 USER’S MANUAL
6-3
Each timer may output a signal on the timer output (TOUT1 or TOUT2) pin when the refer-
ence value is reached, as selected by the output mode (OM) bit of the corresponding TMR.
This signal can be an active-low pulse or a toggle of the current output, under program con-
trol. The output can also be used as an input to the other timer, resulting in a 32-bit timer.
Each timer has a 16-bit TCR, which is used to latch the value of the counter when a defined
transition (of TIN1 or TIN2) is sensed by the corresponding input capture edge detector. The
type of transition triggering the capture is selected by the capture edge (CE) bits in the cor-
responding TMR. Upon a capture or reference event, the corresponding TER bit is set, and
a maskable interrupt is issued.
6.2.2 Software Watchdog Timer
A software watchdog timer is used to protect against system failures by providing a means
to escape from unexpected input conditions, external events, or programming errors. The
third 16-bit timer block is used for this purpose. Once started, the software watchdog timer
must be cleared by software on a regular basis so that it never reaches its timeout value.
Upon reaching the timeout value, the assumption is made that a system failure has
occurred, and the software watchdog logic initiates a reset of the MC68307.
The software watchdog timer counts from zero to a maximum of 32768 (16.67 seconds at
16.00 MHz) with a resolution or step size of 8192 clock periods (0.5 ms at 16.00 MHz). This
timer uses a 16-bit counter with an 8-bit prescaler value.
The software watchdog timer uses the system clock divided by 16 as the input to the pres-
caler. The prescaler circuitry divides the clock input by a fixed value of 256. The output of
this prescaler circuitry is connected to the input of the 16-bit counter. Since the least signif-
icant bit of the WCN is not used in the comparison with the WRR reference value, the effec-
tive value of the prescaler is 512.
The timer counts until the reference value is reached and then starts a new time count imme-
diately. Upon reaching the reference value, the counter asserts an internal output to the
MC68307 reset logic. The reset source bits (RS1-RS0) in the system control register (SCR)
are updated with the cause of reset being indicated as software watchdog. Refer to Section
5.2.1.2 System Control Register (SCR) for further details of the RSx bits.
The value of the timer can be read any time.