參數(shù)資料
型號： MC68MH360VR33LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 105/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
QMC Supplement
2.4.2 Channel-Specic Transparent Parameters
Table 2-10 describes the channel-specic transparent parameters. Boldfaced parameters
must be initialized by the user.
Table 2-9. RSTATE Field Descriptions for 860MH (HDLC)
Field
Name
Description
0–1
—
0
2—
1
3
MOT
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
4—
0
5–7
AT[1–3]
Address type—This eld contains the address type for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Address types are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
Table 2-10. Channel-Specific Transparent Parameters
Offset
Name
Width
Description
00
TBASE
16
Tx buffer descriptor base address—Denes the offset of the channel’s transmit BD
table relative to MCBASE, host-initialized. See Figure 2-2.
02
CHAMR
16
Channel mode register. See Section 2.4.2.1, “CHAMR—Channel Mode Register
(Transparent Mode).”
04
TSTATE
32
Tx internal state —TSTATE denes the internal Tx state.
Host-initialized to 0x3800
_0000—FC = 8, Motorola mode for MH360.
Host-initialized to 0x3000
_0000—AT = 0, Motorola mode for 860MH.
Initialize before enabling the channel. See Section 2.4.2.2, “TSTATE—Tx Internal
State (Transparent Mode).”
08
32
Tx internal data pointer—Points to current absolute address of channel.
0C
TBPTR
16
Tx buffer descriptor pointer (host-initialized to TBASE before enabling the channel
or after a fatal error before reinitializing the channel)—Contains the offset of
current BD relative to MCBASE. See Table 2-1. MCBASE + TBPTR gives the
address for the BD in use.
0E
16
Tx internal byte count—Number of remaining bytes
10
TUPACK
32
(Tx temp) Unpack 4 bytes from 1 long word
14
ZISTATE
32
Zero-insertion machine state (host-initialized to 0x0000
_0100)—Contains the
previous state of the zero-insertion state machine.
18
RES
32
1C
INTMSK
16
Channel’s interrupt mask ags. See Figure 2-9.
1E
BDFlags
16
Temp
20
RBASE
16
Receive buffer descriptor base offset—Denes the offset of the channel’s 64-Kbyte
receive BD table relative to MCBASE. Host-initialized. See also Figure 2-2.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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