參數(shù)資料
型號(hào): MC68MH360VR33LR2
廠商: Freescale Semiconductor
文件頁數(shù): 75/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
Chapter 1.Overview
Figure 1-3. Internal Routing for Ethernet-to-BRI Bridge Using MC68EN360
The following example shows how an MC68MH360 can implement the BRI using only one
SCC, leaving SCC3 and SCC4 available to run other protocols such as frame relay over
HDLC and another Ethernet link, on SCC1, to the LAN. The QMC protocol allows all three
channels B1, B2, and D to be routed to SCC2 using the TSA. The rst byte (B1) is routed
to logical channel 1, the second byte (B2) to logical channel 2, and the third byte to logical
channel 3, of which only the rst 2 bits represent the D channel as illustrated in Figure 1-4
and Figure 1-5. This routing is dened in the QMC time slot assignment tables. The rst
advantage of the QMC protocol is that it releases SCCs to run other protocols. The second
advantage is highlighted in the next example.
E
B1B2D
U
Memory
EN360
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
NMSI
TSA
Ethernet
UART
BRI ISDN
B1
B2
D
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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