- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4005 > MC68MH360VR33LR2 (Freescale Semiconductor)IC MPU QUICC 33MHZ 357-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68MH360VR33LR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 96/158頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)當(dāng)前第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)
QMC Supplement
In Figure 2-5, each SCC has its own pointer, Rx_S_PTR_2 and Rx_S_PTR_3, addressing
SCC2’s time slot assignment table. This table only needs to be present once in one of the
SCC2’s global parameter area. Rx_S_PTR_2 points to the start of the table, address SCC
base + 20. The 16 logical channels from SCC2 are located in the rst 16 entries of the table.
The entry for logical channel 30 has the wrap bit (W) set, causing the CPM to wrap back
to logical channel 0 on reception of the next byte routed to SCC2. Rx_S_PTR_3 addresses
SCC base + 40, the start of the 16 entries for SCC3. The entry for logical channel 31 has
the wrap bit (W) set, causing the CPM to wrap back to logical channel 1 on reception of the
next byte routed to SCC3. Each entry within the table has a channel pointer to a logical
channel. It is important that different SCCs do not point to the same logical channel.
The TSATTx is also located in SCC2’s parameter RAM. This means that the area reserved
for the TSA tables in SCC3’s parameter RAM is free for alternative use.
A second scenario is depicted in Figure 2-6. A 4.096-Mbps TDM link is fed directly into
the TSA. Again, within the SI RAM, the even channels (byte-wide) are muxed to SCC3 and
the odd channels are muxed to SCC2. This arrangement is used to spread the load over two
SCCs. Another reason this method may be used is to facilitate separate routing for the Rx
and Tx logical channels. This requires two 64-entry tables that require 256 bytes, but only
128 bytes are allocated in the parameter RAM of an SCC for time slot assignment tables.
In this case, the Rx table is located in SCC2’s parameter RAM, and the TX table is located
in SCC3’s parameter RAM, making most efcient use of memory.
Changes on the y are easily accomplished by setting or clearing the valid bit for each time
slot. Changes to the mask bits can also be made on the y. This does not cause any problems
to the QMC microcode itself, but may cause protocol errors on the channel in question
depending on when this change is done.
It is possible to have a time slot assignment table for every SCC in its corresponding RAM
page and have all of the TDM routed to the different SCCs. This gives the user a very
exible system that can be changed on the y without disconnecting the TDM interface. In
this case the user must ensure that no collisions occur on the transmit lines from several
SCCs.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68MH360VR25LR2 | IC MPU QUICC 25MHZ 357-PBGA |
| MC68MH360VR25L | IC MPU QUICC 25MHZ 357-PBGA |
| MC68MH360CVR25L | IC MPU QUICC 25MHZ 357-PBGA |
| HMC40DTEI | CONN EDGECARD 80POS .100 EYELET |
| FMC50DRAS-S734 | CONN EDGECARD 100PS .100 R/A SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68MH360ZP25L | 功能描述:IC MPU 32BIT QUICC 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68MH360ZP25LR2 | 功能描述:IC MPU QUICC 25MHZ 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68MH360ZP25VL | 功能描述:IC MPU QUICC ETHER 25MHZ 357PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68MH360ZP33K | 制造商:Freescale Semiconductor 功能描述:MULTI HDLC QUICC32 - Trays |
| MC68MH360ZP33L | 功能描述:IC MPU 32BIT QUICC 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。