參數(shù)資料
型號： MC68MH360VR33LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 148/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Illustrations
ILLUSTRATIONS
Figure
Number
Title
Page
Number
1-1
QMC Channel Addressing Capability ............................................................................. 1-2
1-2
Ethernet-to-BRI Bridge Using MC68EN360................................................................... 1-6
1-3
Internal Routing for Ethernet-to-BRI Bridge Using MC68EN360.................................. 1-7
1-4
Ethernet-to-BRI Bridge Using MC68MH360 ................................................................. 1-8
1-5
Internal Routing for Ethernet-to-BRI Bridge Using MC68MH360 ................................ 1-8
1-6
Ethernet-to-PRI Bridge Using MPC860MH.................................................................... 1-9
1-7
Internal Routing for Ethernet-to-PRI Bridge Using MPC860 ......................................... 1-9
1-8
Frame Structures for E1/CEPT and T1 TDM Interfaces ............................................... 1-12
1-9
MC68MH360 Connection to a TDM Bus ..................................................................... 1-13
2-1
MC68MH360 and MPC860MH Internal Memory Structures......................................... 2-1
2-2
QMC Memory Structure .................................................................................................. 2-2
2-3
Time Slot Assignment Table ........................................................................................... 2-8
2-4
Time Slot Assignment Table for 64-Channel Common Rx and Tx Mapping............... 2-10
2-5
Rx Time Slot Assignment Table for 32 Channels over Two SCCs............................... 2-11
2-6
Time Slot Assignment Tables for 64 Channels over 2 SCCs ........................................ 2-13
2-7
CHAMR—Channel Mode Register (HDLC) ................................................................ 2-15
2-8
TSTATE—Tx Internal State (HDLC) ........................................................................... 2-17
2-9
INTMSK and Interrupt Table Entry (HDLC) ................................................................ 2-18
2-10
RSTATE—Rx Internal State (HDLC)........................................................................... 2-19
2-11
CHAMR—Channel Mode Register (Transparent Mode).............................................. 2-21
2-12
TSTATE—Tx Internal State (Transparent Mode)......................................................... 2-23
2-13
INTMSK and Interrupt Table Entry (Transparent Mode) ............................................. 2-24
2-14
Examples of Different T1 Time Slot Allocation............................................................ 2-27
2-15
RSTATE—Rx Internal State (Transparent Mode) ........................................................ 2-28
3-1
Command Register (CR).................................................................................................. 3-1
4-1
Circular Interrupt Table in External Memory .................................................................. 4-1
4-2
SCC Event Register ......................................................................................................... 4-4
4-3
SCCM Register ................................................................................................................ 4-5
4-4
Interrupt Table Entry........................................................................................................ 4-5
4-5
Channel Interrupt Flow .................................................................................................... 4-8
5-1
Receive Buffer Descriptor (RxBD) ................................................................................. 5-1
5-2
Nonoctet Alignment Data ................................................................................................ 5-4
5-3
Transmit Buffer Descriptor (TxBD) ................................................................................ 5-5
5-4
Relation between PAD and NOF..................................................................................... 5-6
5-5
MC68MH360 Internal Memory....................................................................................... 5-8
5-6
SCC2 Parameter RAM Overlap Example........................................................................ 5-8
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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