參數(shù)資料
型號： MC68MH360VR33LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 128/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Chapter 5. Buffer Descriptors
Chapter 5
Buffer Descriptors
50
QMC buffer descriptors are located within 64 Kbytes in external memory; see Figure 2-2.
Each buffer descriptor contains key information about the buffer it denes.
The rst two sections describe the contents of the receive and transmit buffer descriptors
for the QMC protocol.
The third section discusses the placement of QMC and non-QMC buffer descriptors in
internal and external memory.
5.1 Receive Buffer Descriptor
Figure 5-1 shows a receive buffer descriptor.
Notes: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Entries in boldface must be initialized by the user.
Figure 5-1. Receive Buffer Descriptor (RxBD)
Table 5-1 describes the individual elds of a receive buffer descriptor. Boldfaced entries
must be initialized by the user.
0123456789
10
11
12
13
14
15
OFFSET + 0
E
—
WI
LF
CM
—
UB
—
LG
NO
AB
CR
—
OFFSET + 2
DATA LENGTH
OFFSET + 4
Rx DATA BUFFER POINTER
OFFSET + 6
Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions
Field
Name
Description
0
E
Empty
0 The data buffer associated with this buffer descriptor has been lled with received data, or
data reception has been aborted due to an error. The core is free to examine or write to any
eld of this RxBD. The CPM does not use this buffer descriptor again while the empty bit
remains zero.
1 The data buffer associated with this buffer descriptor is empty, or reception is currently in
progress. This RxBD and its associated receive buffer are owned by the CPM. If E = 1, the
CPU core should not write to any eld of this RxBD.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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