14-2
MCF5249UM
MOTOROLA
DMA Signal Description
14.1
DMA FEATURES
Four fully independent programmable DMA controller module channels/bus modules
Auto-alignment feature for source or destination accesses
Dual-address transfer capability
Programmable hardware request lines from the audio module and UART going to all 4 DMA channels
Channels 2 and 3 request signals may be connected to the interrupt lines of UART0 and UART1,
respectively
Channel arbitration on transfer boundaries
Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
Burst and cycle steal transfers
Independent transfer widths for source and destination
Independent source and destination address registers
Data transfer in two clocks
14.2
DMA SIGNAL DESCRIPTION
This section contains a brief description of the DMA module signals that provide handshake control for
either a source or destination external device.
Table 14-1 summarizes these handshake signals
.
14.2.1
DMA REQUEST
These internal signals, REQUEST[3:0], are DMA request inputs. There is one input for each of the 4 DMA
channels. The request sources are selectable by programming the DMAROUTE register. Each DMA
channel is programmable individually.
The internal signals are asserted by a peripheral device to request an operand transfer between that
peripheral and memory.
14.3
DMA MODULE OVERVIEW
The DMA controller module usually transfers data at rates much faster than the ColdFire core under
software control can handle. The term DMA refers to the ability for a peripheral device to access memory
in a system in the same manner as a microprocessor. DMA operations can greatly increase overall system
performance.
The DMA module consists of four independent channels. The term DMA is used throughout this section to
reference any of the four channels, as they are all functionally equivalent. It is impossible to implicitly
address all four DMA channels at the same time. The MCF5249 on-chip peripherals do not support the
single-address transfer mode.
DMA requests can be generated by the processor writing to the START bit in the DMA control register or
generated by an on-chip peripheral device asserting one of the REQUEST signals. The processor can
program the amount of bus bandwidth allocated for the DMA for each channel. The DMA channels support
continuous and cycle-steal transfer modes.
Table 14-1 DMA Signals
SIGNAL NAME
DIRECTION
DESCRIPTION
REQUEST[3:0]
In
DMA Request signal coming from
internal modules
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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