Processor Interface Overview
MOTOROLA
Audio Functions
17-27
17.4.3
PDIR AND PDOR FIELD FORMATTING
Each PDIR, PDOR 32-bit register contains only 20 relevant data bits. Formatting is done as follows:
Note:
1. L18 is bit 18 of left sample, ~L19 is inverse of bit 19 of left sample, R18 is bit 18 of right sample.
Note:
2. If incoming/outgoing interface use 16, 18 bits, data is aligned at the MSB side. LSB ‘s D1-D0 or D3-D0 will read all-zero. Written values are
disregarded.
Note:
3. PDOR3, PDIR2 use only 16 MSB of both left and right.
Note:
4. Inversion of MSB ‘s L19 and R19 translates the format from 2-complement to unsigned.
(The continuous range e.g. -0x8000 to +7FFF is translated to 0 to +0xFFFF)
17.4.4
OVERRUN AND UNDERRUN WITH PDIR AND PDOR REGISTERS
All PDOR and PDIR registers have different FIFOs for left and right channel. As a result, there is always
the possibility that left and right FIFOs may go out of sync due to fifo underruns and fifo overruns that affect
only one part (left or right) of any fifo. To prevent this from happening, two hardware mechanisms are
available:
1. If PDIR1, PDIR2, or PDIR3 fifo overrun occurs on, as an example, the right half of the FIFO, the
sample that caused the overrun is not written to the right half (due to overrun). Special hardware
will make sure the next sample is not written to the left half of the FIFO. If the overrun occurs on the
left half of the fifo, the next sample is not written to the right half of the FIFO.
2. If IIS1 or IIS2 Tx fifo, or EBU Tx fifo underruns on, for example, the right half of the FIFO, no sample
leaves that fifo. (because it was already empty.) Special hardware ensures that the next sample
read from the left fifo will not leave the fifo. (No read strobe is generated). If the underrun occurs on
the left half of the FIFO, next read strobe to the right fifo is blocked.
Table 17-26 PDIR1-L, PDIR3-L, PDOR1-L, PDOR2-L Formatting
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
~L19
L19
L18
L17
L16
L15
L14
L13
L12
L11
L10
L9
L8
L7
L6
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
L5
L4
L3
L2
L1
L0
0
Table 17-27 PDIR1-R, PDIR3-R, PDOR1-R, PDOR2-R Formatting
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
~R19
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
R5
R4
R3
R2
R1
R0
0
Table 17-28 PDIR2, PDOR3 Formatting
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
L19
L18
L17
L16
L15
L14
L13
L12
L11
L10
L9
L8
L7
L6
L5
L4
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
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