17-30
MCF5249UM
MOTOROLA
Processor Interface Overview
17.4.6
AUDIO INTERRUPTS
17.4.6.1
AudioTick Interrupts
The audio tick interrupt is an interrupt to sustain an interrupt routine that is synchronous with one of the
audio interfaces, but not directly related to any FIFO being full or empty. Two fields control how this
interrupt is generated:
1. The source field controls the source event.
2. The count field controls the number of events (sample pairs) between any two audioTick interrupts.
For example, if the source is set to IIS1 Tx fifo / Read, and count is set to three, the interrupt will pulse after
every three read strobes to the IIS1 Tx fifo. Even if the fifo is in reset state, the interrupt will continue
running.
17.4.6.2
PDIR1, PDIR2, and PDIR3, Exceptions
With FIFOs feeding data to PDIR registers, three exceptions are associated.
1. Full
2. Under/over
3. Resync
When the Full condition is set for processor data input registers, the MCF5249 processor should read data
from the FIFO, before overrun occurs (this is within 1/2 sample period). Reading of data should be done
using 32-bit operands (ex. MOVE.L instruction). When Full is set, and the FIFO contains, for example six
samples, it is acceptable for the software to read the first six samples from the LEFT address, followed by
six samples from the RIGHT address, or six samples from the RIGHT address, followed by six samples
from the LEFT address, or one sample LEFT, followed by one sample RIGHT repeated six times. There is
no order specified.
The implementation for PDIR1 is a double FIFO, one for left and one for right. The Full condition is set
when both FIFOs are full. The Underrun/Overrun condition is set when one of the FIFOs actually underrun
or overrun. The resync interrupt is set when the hardware took special action to resynchronize left and right
FIFOs.
17.4.6.3
PDOR1, PDOR2, and PDOR3 Exceptions
Three exceptions are associated with FIFOs that can be written from PDOR1, PDOR2, PDOR3:
1. Empty
2. Under/over
3. Resync
When the Empty condition is set for processor data output registers, the ColdFire processor should write
data to the FIFO, before underrun occurs. Writing of data should be done using MOVE LONG or MOVEM
instructions, in any case with long-word oriented instructions. When Empty is set, and, for example, six
samples need to be written, it is acceptable for the software to write first six samples from the LEFT
address, followed by six samples from the RIGHT address, or one sample LEFT, followed by one sample
RIGHT repeated six times.
Note: The left should be written before the right.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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