17-32
MCF5249UM
MOTOROLA
Processor Interface Overview
17.4.6.4
Audio Interrupt Routines and Timing
Usually, the MCF5249 processor will run an audio interrupt routine. Every time the audio interrupt routine
runs, it will process 2, 3, or 4 audio samples, and send this many samples to one or more PDOR output
registers. Also, the audio interrupt routine will read one or more PDIR registers until empty.
In the audio interrupt routine, typically at the beginning, the PDIR registers are read until empty, while the
PDOR registers are written at the end of the routine when all calculations are completed. Due to this
calculation latency, there is a delay between entering the audio interrupt routine and the filling of the
transmit FIFOs.
Due to this delay, it is difficult to “fire” the audio interrupt routine on a transmit FIFO empty interrupt.
Because of the extra delay before the data is written, the transmit fifo will underrun before any data is
written.
To make it easy for the programmer, the audioTick interrupt was added. To start the audio interrupt
routine, use the following sequence:
1. Reset the transmit FIFOs
2. Program the transmit FIFOs to correct source, de-assert reset on transmit FIFOs
3. Reset the PDIR FIFOs
4. Load audio interrupt routine in on-chip SRAM
5. Release reset for the PDIR FIFOs and enable audioTick interrupt
The transmit FIFOs have a special feature. After the software releases the reset to them, they will stay in
reset until the audio Interrupt Routine writes data to them for the first time. So, during Step 2 of above
mentioned start-up procedure, all transmit data out FIFOs are set in reset, with one sample remaining.
They will stay in this state, until the audio Interrupt Routine writes data to them. At this point in time, they
are then filled up with extra 2,3, or 4 samples to a total of 3,4, or 5 samples. Also, the first data write to the
FIFOs releases the reset, and starts transmission of FIFO data on the corresponding transmit output.
(IIS1, IIS2 or IEC958). The next time that data is written to the FIFOs in the audioTick interrupt routine, 2,3,
or 4 samples have been transmitted and the FIFO is ready to accept new data.
To work properly, the jitter from one audioTick write point to the next is important. Jitter should be lower
than 1 sample period if data is written in groups of 2 or 3 samples to the transmit FIFOs, and lower than 1/2
sample period if data is written in groups of 4 samples to the transmit FIFOs.
The receive FIFOs (PDIR) don’t have an auto-reset-de-assert mechanism, and should be released out of
reset just before enabling audioTick interrupt.
Figure 17-8 shows the timing (relative to the Word Clock) of the Empty, Under-run, and Audio Tick
interrupts. Each FIFO holds up to six audio samples (left and right).
4
iis1TxEmpty
IIS 1 transmit fifo empty
write to FIFO
3
iis2TxEmpty
IIS 2 transmit fifo empty
write to FIFO
2
ebuTxEmpty
IEC958 transmit fifo empty
write to FIFO
1
PDIR2 full
Processor data input full
read from PDIR2
0
PDIR1 full
Processor data input full
read from PDIR1
Table 17-31 Interrupt Register Description (0x94, 0x98) (Continued)
BIT
INTERRUPT NAME
DESCRIPTION
HOW TO CLEAR
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.