Exception Processing Overview
MOTOROLA
ColdFire Core
3-7
3.3
EXCEPTION PROCESSING OVERVIEW
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
provide a simplified exception processing model. The next section details the model.Differences from
previous 68000 Family processors include:
A simplified exception vector table
Reduced relocation capabilities using the vector base register
A single exception stack frame format
Use of a single self-aligning system stack
ColdFire processors use an instruction restart exception model but do require more software support to
recover from certain access errors.
Exception processing is comprised of four major steps and is defined as the time from the detection of the
fault condition to the fetch of the first handler instruction has been initiated.
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The occurrence of an interrupt exception also
forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current
interrupt request.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on the exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a peripheral
device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level
encoded in the address.
3. The processor saves the current context by creating an exception stack frame on the system stack.
The V2 Core supports a single stack pointer in the A7 address register; therefore, there is no notion
of separate supervisor or user stack pointers. As a result, the exception stack frame is created at a
0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a
simplified fixed-length stack frame for all exceptions. The exception type determines whether the
program counter placed in the exception stack frame defines the location of the faulting instruction
(fault) or the address of the next instruction to be executed (next).
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1 Mbyte boundary. This instruction address is generated
by fetching an exception vector from the table located at the address defined in the vector base
register. The index into the exception table is calculated as (4 x vector number). Once the
exception vector has been fetched, the contents of the vector determine the address of the first
instruction of the desired handler. After the instruction fetch for the first opcode of the handler has
been initiated, exception processing terminates and normal instruction processing continues in the
handler.
ColdFire 5200 processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see
Table 3-6). The table contains 256 exception vectors where the first 64 are defined by Motorola and the
remaining 192 are user-defined interrupt vectors.
The V2 Core processor inhibits sampling for interrupts during the first instruction of all exception handlers.
This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
contained in the status register.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.