19-38
MCF5249UM
MOTOROLA
Real-Time Debug Support
BKD[18]
The Disable the Normal BKPT Input Signal Functionality bit is used to disable the normal
BKPT input signal functionality, and allow the assertion of this pin to generate a debug
interrupt. If set, the assertion of the BKPT pin is treated as an edge-sensitive event.
Specifically, a high-to-low edge on the BKPT pin generates a signal to the processor
indicating a debug interrupt. The processor makes this interrupt request pending until the
next sample point occurs. At that time, the debug interrupt exception is initiated. In the
ColdFire architecture, the interrupt sample point occurs once per instruction. There is no
support for any type of “nesting” of debug interrupts.
PCD[17]
If set, the PSTCLK Disable bit disables the generation of the PSTCLK output signal, and
forces this signal to remain quiescent.
IPW[16]
If set, the Inhibit Processor Writes to Debug Registers bit inhibits any processor-initiated
writes to the debug module’s programming model registers. This bit can only be modified by
commands from the external development system.
MAP[15]
If set, the Force Processor References in Emulator Mode bit forces the processor to map all
references while in emulator mode to a special address space, TT = $2, TM = $5 or $6. If
cleared, all emulator-mode references are mapped into supervisor code and data spaces.
TRC[14]
If set, the Force Emulation Mode on Trace Exception bit forces the processor to enter
emulator mode when a trace exception occurs.
EMU[13]
If set, the Force Emulation Mode bit forces the processor to begin execution in emulator
DDC[12:11]
The 2-bit Debug Data Control field provides configuration control for capturing operand data
for display on the DDATA port. The encoding is:
00 = no operand data is displayed
01 = capture all M-Bus write data
10 = capture all M-Bus read data
11 = capture all M-Bus read and write data
In all cases, the
DDATA port displays the number of bytes defined by the operand reference
size. For example, byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one
UHE[10]
The User Halt Enable bit selects the CPU privilege level required to execute the HALT
instruction.
0 = HALT is a privileged, supervisor-only instruction
1 = HALT is a non-privileged, supervisor/user instruction
BTB[9:8]
The 2-bit Branch Target Bytes field defines the number of bytes of branch target address to
be displayed on the
DDATA outputs. The encoding is:
00 = 0 bytes
01 = lower two bytes of the target address
10 = lower three bytes of the target address
11 = entire four-byte target address
Table 19-34 Configuration/Status Bit Descriptions (Continued)
BIT NAME
DESCRIPTION
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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