Processor Exceptions
MOTOROLA
ColdFire Core
3-11
3.5.5
PRIVILEGE VIOLATION
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. Refer to the ColdFire Programmer’s Reference Manual for lists of supervisor- and
user-mode instructions.
3.5.6
TRACE EXCEPTION
To aid in program development, the V2 processors provide an instruction-by-instruction tracing capability.
While in trace mode, indicated by the assertion of the T bit in the status register (SR[15] = 1), the
completion of an instruction execution signals a trace exception. This functionality allows a debugger to
monitor program execution.
The single exception to this definition is the STOP instruction. When the STOP opcode is executed, the
processor core waits until an unmasked interrupt request is asserted, then aborts the pipeline and initiates
interrupt exception processing.
Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. For
example, consider the execution of a TRAP instruction while in trace mode. The processor will initiate the
TRAP exception and then pass control to the corresponding handler. If the system requires that a trace
exception be processed, it is the responsibility of the TRAP exception handler to check for this condition
(SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from
the original exception.
3.5.7
DEBUG INTERRUPT
This exception is generated in response to a hardware breakpoint register trigger. The processor does not
generate an IACK cycle but rather calculates the vector number internally (vector number 12).
3.5.8
RTE AND FORMAT ERROR EXCEPTIONS
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire 5200 processor, any attempted execution of an RTE where the format is not
equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created
without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from 68000
applications. On 680x0 family processors, the SR was located at the top of the stack. On those
processors, bit[30] of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE
is attempted using this “old” format, it generates a format error on a ColdFire 5200 processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented
address after the fetch of the first longword, and then (4) transfers control to the instruction address
defined by the second longword operand within the stack frame.
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Freescale Semiconductor, Inc.
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