參數(shù)資料
型號(hào): ML9050
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
中文描述: 132通道液晶內(nèi)置液晶點(diǎn)陣顯示RAM的驅(qū)動(dòng)程序
文件頁(yè)數(shù): 13/71頁(yè)
文件大小: 472K
代理商: ML9050
Semiconductor
ML9050/9051
13/71
PEDL9050-02
Line address circuit
The line address circuit is used for specifying the line address corresponding to the COM output
when displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the
topmost line in the display (COM0 output in the normal display state of the common output, and
COM63 output and COM47 output for the ML9050 and the ML9051, respectively, in the reverse
display stage) is specified using the display start line address set command. The display area
is 65 lines and 49 lines for the ML9050 and the ML9051, respectively, in the direction of increasing
line address from the specified display start line address. It is possible to carry out screen
scrolling and page changing by dynamically changing the line address using the display start
line address set command.
Display data latch circuit
The display data latch circuit is a latch for temporarily storing the data from the display data
RAM before being output to the LCD drive circuits. Since the commands for selecting normal/
reverse display and turning the display ON/OFF control the data in this latch, the data in the
display data RAM will not be changed.
Oscillator circuit
This is an RC oscillator that generates the display clock. The oscillator circuit is effective only
when M/
S
= "H" and also CLS = "H". The oscillations will be stopped when CLS = "L", and the
display clock has to be input to the CL pin.
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