參數(shù)資料
型號: ML9050
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
中文描述: 132通道液晶內(nèi)置液晶點陣顯示RAM的驅(qū)動程序
文件頁數(shù): 15/71頁
文件大小: 472K
代理商: ML9050
Semiconductor
ML9050/9051
15/71
PEDL9050-02
Display timing generator circuit
This circuit generates the timing signals for the line address circuit and the display data latch
circuit from the display clock. The display data is latched in the display data latch circuit and is
output to the segment drive output pins in synchronization with the display clock. This circuit
generates the timing signals for the line address circuit and the display data latch circuit from the
display clock. The display data is latched in the display data latch circuit and is output to the
segment drive output pins in synchronization with the display clock. The read out of the display
data to the LCD drive circuits is completely independent of the display data RAM access from
the MPU. As a result, there is no bad influence such as flickering on the display even when the
display data RAM is accessed asynchronously during the LCD display. Also, the internal
common timing and LCD frame reversal (FR) signals are generated by this circuit from the
display clock. The drive waveforms of the frame reversal drive method shown in Fig. 5(a) for the
LCD drive circuits are generated by this circuit. Further, the drive waveforms of the line reversal
method shown in Fig. 5(b) can also be generated depending on the issued command.
In the line reversal drive method, it is possible to carry out reverse display drive at every line to
a maximum of 32 lines. Fig. 5(b) shows the waveforms of the 1 line reversal drive method.
RAM
DATA
V
SS
V5
COM1
64 65
1
2
3
4
5
6
V2
V1
V
SS
V4
SEGn
V3
V1
60 61 62 63 64 65
1
2
3
4
5
6
V
SS
V5
COM0
V2
V1
FR
LCDCK
(display clock)
Fig. 5(a) Waveforms in the frame reversal drive method
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