參數(shù)資料
型號: ML9050
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
中文描述: 132通道液晶內(nèi)置液晶點陣顯示RAM的驅(qū)動程序
文件頁數(shù): 31/71頁
文件大小: 472K
代理商: ML9050
Semiconductor
ML9050/9051
31/71
PEDL9050-02
Status read (Read)
A0
0
D7
D6
ADC ON/OFF RESET
D5
D4
D3
0
D2
0
D1
0
D0
0
BUSY
BUSY
When BUSY is '1', it indicates that the internal operations are being made or the LSI is being reset.
Although no command is accepted until BUSY becomes '0', there is no need to check this bit if the
cycle time can be satisfied.
This bit indicates the relationship between the column address and the segment driver.
0: SEG0
SEG131; column address 0H
83H
1: SEG131
SEG0; column address 0H
83H
(Opposite to the polarity of the ADC command.)
This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the display ON/OFF
command.)
0: Display ON
1: Display OFF
This bit indicates that the LSI is being reset due to the
RES
signal or the reset command.
0: Operating state
1: Being reset
ADC
ON/OFF
RESET
Display data write (Write)
This command writes an 8-bit data at the specified address of the display data RAM. Since the
column address is automatically incremented (by +1) after writing the data, the MPU can write
successive display data to the display data RAM.
A0
1
D7
D6
D5
D4
Write data
D3
D2
D1
D0
Display data read (Read)
This command read the 8-bit data from the specified address of the display data RAM. Since the
column address is automatically incremented (by +1) after reading the data, the MPU can read
successive display data from the display data RAM. Further, one dummy read operation is
necessary immediately after setting the column data. The display data cannot be read out when
the serial interface is being used.
A0
1
D7
D6
D5
D4
Read data
D3
D2
D1
D0
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