參數(shù)資料
型號: ML9050
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
中文描述: 132通道液晶內(nèi)置液晶點陣顯示RAM的驅(qū)動程序
文件頁數(shù): 55/71頁
文件大小: 472K
代理商: ML9050
Semiconductor
ML9050/9051
55/71
PEDL9050-02
Parameter
Condition
Rated value
Min
0
0
300
40
15
10
[V
DD
= 2.7 V to 4.5 V, Ta = –40 to +85C]
Unit
Max
140
100
Symbol
t
AH6
t
AW6
t
CYC6
t
DS6
t
DH6
t
ACC6
t
OH6
Applicable
pins
A0
A0
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
ns
t
EWHR
t
EWHW
t
EWLR
t
EWLW
E
Read
Write
Read
Write
Enable H pulse width
120
60
60
60
E
Enable L pulse width
D0 to D7
CL = 100pF
Parameter
Condition
Rated value
Min
0
0
1000
80
30
10
[V
DD
= 1.8 V to 2.7 V, Ta = –40 to +85C]
Unit
Max
280
200
Symbol
t
AH6
t
AW6
t
CYC6
t
DS6
t
DH6
t
ACC6
t
OH6
Applicable
pins
A0
A0
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
ns
t
EWHR
t
EWHW
t
EWLR
t
EWLW
E
Read
Write
Read
Write
Enable H pulse width
240
120
120
120
E
Enable L pulse width
D0 to D7
CL = 100pF
Note 1:
The input signal rise and fall times are specified as 15ns or less.
When using the system cycle time for fast speed, the specified values are (tr+tf)
(t
CYC6
-t
EWLW
-t
EWHW
) or (tr+tf)
(t
CYC6
-t
EWLR
-t
EWHR
).
All timings are specified taking the levels of 20% and 80% of VDD as the reference.
The values of t
EWLW
and t
EWLR
are specified during the overlapping period of
CS1
at
"L" (CS2 = "H") and the "H" level of E.
Note 2:
Note 3:
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