參數(shù)資料
型號： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無鉛汽油電話控制器
文件頁數(shù)： 20/88頁
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
20
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.3
Interrupt controller
In order to service interrupt requests coming from external
events and from the on-chip peripherals the P83CL882
offers a 17 source, two priority level nested interrupt
system. A detailed description of the interrupt process is
given in the following sections. Table 14 shows the
available interrupts with each vector address and Table 15
shows an overview of all the interrupt related SFRs. The
detailed interrupt related SFR description can be found in
Sections 6.3.4 to 6.3.10.
6.3.1
G
ENERAL
Each interrupt vector points to a separate location in
program memory for its service routine. Each source can
be individually enabled or disabled by its corresponding bit
in the Interrupt Enable Registers (IEN0, IEN1 and IEN2).
The priority level is selected via the Interrupt Priority
Registers(IP0,IP1andIP2).Allavailableinterruptscanbe
globally disabled or enabled.
The interrupt controller samples all active sources during
one instruction cycle. Evaluation of the interrupts is then
performed. A priority decoder decides which interrupt is
serviced. Each interrupt has its own vector pointing to an
8 bytes long memory segment.
A low priority interrupt can be interrupted by a high priority
interrupt, but not by another low priority interrupt i.e. only
two interrupt levels are possible.
Between the RETI instruction (Return from Interrupt) and
the execution of a next interrupt at least one instruction of
the lower program level is executed. The interrupt service
with different priorities is shown in Fig.11.
An interrupt is performed with a long subroutine call
(LCALL) to a vector address, which is determined by the
respective interrupt. During LCALL the Program
Counter (PC) is pushed onto the stack. Returning from
interrupt with RETI, the PC is popped from the stack.
In the event of several interrupts with the same priority
level, the order of sequence in which they will be serviced
is determined by the scanning order.
The interrupt highest in the scanning list will always be
served first, interrupts lower in the scanning list will be
served in the order as shown in Fig.12. No interrupt will be
lost.
Table 14
Available interrupts (ordered by vector address)
HW = hardware; SW = software.
SOURCE
SYMBOL
VECTOR
(HEX)
CLEARED
BY
INT 0
Timer 0
INT 1
Timer 1
I
2
C-bus
Timer 2
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
MSK modem
transmitter
MSK mode receiver
Watchdog Timer
X0
T0
X1
T1
S1
T2
X2
X3
X4
X5
X6
X7
X8
X9
MTI
0003
000B
0013
001B
002B
0033
003B
0043
004B
0053
005B
0063
006B
0073
0083
HW
HW
HW
HW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
MRI
WDI
008B
00B3
SW
SW
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P83CL882T/001 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 Ultra Low Power ULP telephony controller
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