參數(shù)資料
型號(hào)： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無(wú)鉛汽油電話控制器
文件頁(yè)數(shù)： 48/88頁(yè)
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
48
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.8.2
D
ATA
S
HIFT
R
EGISTER
(S1DAT)
S1DAT contains a byte of serial data to be transmitted or
a byte which has just been received. The CPU can read
from and write to this 8-bit SFR while it is not in the process
of shifting a byte. This occurs when SIO1 is in a defined
state and the serial interrupt flag is set. Data in S1DAT
remains stable as long as SI is set.
Data in S1DAT is always shifted from right to left: the first
bit to be transmitted is the MSB (bit 7) and after a byte has
been received, the first bit of received data is located at the
MSBofS1DAT.Whiledataisbeingshiftedout,dataonthe
bus is simultaneously being shifted in; S1DAT always
contains the last data byte present on the bus.
Thus, in the event of lost arbitration, the transition from
master transmitter to slave receiver is made with the
correct data in S1DAT. Reset initializes S1DAT to 00H.
S1DAT and the ACK flag form a 9-bit shift register which
shifts in or shifts out an 8-bit byte, followed by an
acknowledge bit.
The ACK flag is controlled by the SIO1 hardware and
cannot be accessed by the CPU. Serial data is shifted
through the ACK flag into S1DAT on the rising edges of
clock pulses on the SCL line.
When a byte has been shifted into S1DAT, the serial data
is available in S1DAT, and the acknowledge bit is returned
by the control logic during the ninth clock pulse. Serial data
is shifted out from S1DAT via a buffer on the falling edges
of clock pulses on the SCL line.
When the CPU writes to S1DAT, the buffer is loaded with
the contents of S1DAT.7 which is the first bit to be
transmitted to the SDA line. After nine serial clock pulses,
the eight bits in S1DAT will have been transmitted to the
SDA line, and the acknowledge bit will be present in ACK.
Note that the eight transmitted bits are shifted back into
S1DAT.
Table 60
Data Shift Register (SFR address DAH)
Table 61
Description of S1DAT bits
7
6
5
4
3
2
1
0
S1DAT.7
S1DAT.6
S1DAT.5
S1DAT.4
S1DAT.3
S1DAT.2
S1DAT.1
S1DAT.0
BIT
SYMBOL
DESCRIPTION
7 to 1
S1DAT.[7:0]
Eight data bits, to be transmitted or just received. A logic 1 in S1DAT corresponds to a
HIGH level on the I
2
C-bus, and a logic 0 corresponds to a LOW level on the bus. Serial
data transmission of S1DAT is MSB first.
相關(guān)PDF資料
PDF描述
P83CL883T TELX microcontrollers for CT0 handset/basestation applications
P83CL884T TELX microcontrollers for CT0 handset/basestation applications
P87CL883T TELX microcontrollers for CT0 handset/basestation applications
P87CL884T TELX microcontrollers for CT0 handset/basestation applications
P8503BMG N-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P83CL882T/001 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 Ultra Low Power ULP telephony controller
P83CL883T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TELX microcontrollers for CT0 handset/basestation applications
P83CL883T/XXX 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MICROCONTROLLER|8-BIT|8051 CPU|CMOS|SOP|28PIN|PLASTIC
P83CL884T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TELX microcontrollers for CT0 handset/basestation applications
P83CL884T/XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*