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參數資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數： | 23/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
23
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.3.2
I
NTERRUPT PROCESS
1.
Sample the interrupt lines.
The interrupt lines are
latched at the beginning of each instruction cycle.
Analyse the requests.
The sampled interrupt lines
will be analysed with respect to the relevant Interrupt
Enable Register (IENx) and Interrupt Priority
Register (IPx). The process will deliver the vector of
the highest interrupt request and the priority
information. Depending on the interrupt level and the
priorityof the interrupt in progress, an interrupt request
to the core is performed. The vector address will be
passed to the core process.
Interrupt request to core.
a)
Level 0:
the interrupt request to the core is
performed, when at least one instruction is
performed since the RETI from Level 1.
b)
Level 1:
the interrupt request is performed, when
at leastone instruction isperformed since theRETI
from Level 21 and the request has high priority.
c)
Level 20:
no request is performed.
d)
Level 21:
no request is performed.
Update the interrupt level.
a)
Level 0:
in the event of a high priority interrupt the
new level will be Level 20; if it is a low priority
interrupt, the new level will be Level 1.
b)
Level 1:
in the event of a high priority interrupt, the
new level will be Level 21; a low priority interrupt is
not performed, the level is unchanged; on RETI the
new level will be Level 0.
c)
Level 20:
on RETI; the new level is Level 0.
d)
Level 21:
on RETI; the new level is Level 1.
e)
Level 1:
on RETI; the new level is Level 0.
f)
Level 0:
the new level is Level 0.
2.
3.
4.
5.
Clearing the flags.
During the forced LCALL the
interrupt flag of the relevant interrupt is cleared by
hardware, if applicable, otherwise by software.
Idle and Power-down.
When Idle (PCON.0) or
Power-down (PCON.1) is set, the interrupt controller
waits for the wake-up signal. Because the interrupt
controller is waiting for wake-up, all activity in the
circuit will be stopped, thus no handshake can be
completed. The wake-up signal for Idle is the OR of all
the interrupt request bits and the reset. For
Power-down the wake-up signal is built only with the
Port 1 external interrupt request flags (X2 to X9) and
the reset (external reset).
6.
6.3.3
P
ORT
1
INTERRUPTS
Eight Port 1 lines can be used as external interrupt inputs
(X2 to X9). When enabled by IEN1 SFR, each of these
interrupts may wake-up the device from Idle or
Power-down. These external interrupts can each
independently be programmed to positive and negative
polarity and to edge and level sensitivity by setting SFR
IX1 and ISE1 (see Table 34). Figure 12 shows
programming of polarity and sensitivity of the Port 1
interrupts.WhenavalideventoccursonanenabledPort 1
interrupt, the corresponding bit in the Interrupt Request
Flags Register will be set (IRQ1). The interrupt request
flags must be cleared by software.
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相關代理商/技術參數 |
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|---|---|
| P83CL882T/001 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 Ultra Low Power ULP telephony controller |
| P83CL883T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TELX microcontrollers for CT0 handset/basestation applications |
| P83CL883T/XXX | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MICROCONTROLLER|8-BIT|8051 CPU|CMOS|SOP|28PIN|PLASTIC |
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| P83CL884T/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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